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91. 发明专利

JP2004118922A Magnetic random access memory 有权
公开(公告)号：JP2004118922A
公开(公告)日：2004-04-15
申请号：JP2002279744
申请日：2002-09-25
申请人： Toshiba Corp , 株式会社東芝
发明人： FUJITA KATSUYUKI , IWATA YOSHIHISA
IPC分类号： G11C11/15 , G11C8/08 , G11C11/16
CPC分类号： G11C8/08 , G11C11/16
摘要： PROBLEM TO BE SOLVED: To prevent incorrect writing caused by an excessive flow of writing electric current.
SOLUTION: One end of a writing wordline WWL1 is connected to a decoder driver unit 12-1. The decoder driver unit 12-1 consists of P channel MOS transistors P1 and P2, an N channel MOS transistor N1, a differential amplifier DA3 and a NAND circuit ND1. When all of WRITE, CHRDY and RA become "H", an output signal of NAND circuit ND1 becomes "H", and the writing electric current flows into the writing wordline WWL1. At this time, a value of the writing electric current is restricted to a value which does not to exceed a VLIMIT/R1 by a differential amplifier DA3. The R1 is a resistance of a conductor of the writing wordline WWL.
COPYRIGHT: (C)2004,JPO

92. 发明专利

JP2003331574A Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：JP2003331574A
公开(公告)日：2003-11-21
申请号：JP2002140499
申请日：2002-05-15
申请人： Toshiba Corp , 株式会社東芝
发明人： IWATA YOSHIHISA , NAKAJIMA KENTARO
IPC分类号： G11C11/15 , G11C11/16
CPC分类号： G11C11/16
摘要： PROBLEM TO BE SOLVED: To stabilize a write characteristic by adjusting a pulse waveform of a write current. SOLUTION: Setting data deciding supply/cut-off timing, amplitude, and its temporal variation (current waveform) of a write-word/bit-line-current is registered in a setting circuit 23. A write-current waveform control circuit 24 generates a write word line drive signal WWLDRV, write word line synch- signal WWLSNK, write bit line drive signal WBLDRV, and a write bit line synch-signal WBLSNK based on this setting data. A current waveform of the write word/bit line current is controlled for each chip or each memory cell array. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过调整写入电流的脉冲波形来稳定写入特性。解决方案：设置电路23中记录写入/位线电流的设定数据决定供给/截止定时，幅度及其时间变化（电流波形）。写入电流波形控制基于该设定数据，电路24产生写字线驱动信号WWLDRV，写字线同步信号WWLSNK，写位线驱动信号WBLDRV和写位线同步信号WBLSNK。对每个芯片或每个存储单元阵列控制写入字/位线电流的电流波形。版权所有（C）2004，JPO

93. 发明专利

JP2003318366A Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：JP2003318366A
公开(公告)日：2003-11-07
申请号：JP2002118215
申请日：2002-04-19
申请人： Toshiba Corp , 株式会社東芝
发明人： ASAO YOSHIAKI , IWATA YOSHIHISA , SAITO YOSHIAKI , YODA HIROAKI , UEDA TOMOMASA , AMANO MINORU , TAKAHASHI SHIGEKI , KISHI TATSUYA
IPC分类号： H01L27/105 , H01L21/8246 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To allow a write magnetic field to efficiently work on a TMR element of an MRAM. SOLUTION: Immediately under the TMR element 23, a write word line 20B is disposed. The write word line 20B is extended in an X direction, and side faces and the bottom face of the write word line 20B are covered with a yoke material 25B having high magnetic permeability. The yoke material 25B sinks below the top face of the write word line 20B. Immediately above the TMR element 23, a data selection line (read/write bit line) 24 is disposed. The data selection line 24 is extended in a Y direction which crosses the X direction. The top face of the data selection line 24 is covered with a yoke material 27 having high magnetic permeability. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：允许写入磁场有效地工作在MRAM的TMR元件上。解决方案：立即在TMR元件23下方设置写字线20B。写字线20B在X方向上延伸，并且写字线20B的侧面和底面被具有高磁导率的磁轭材料25B覆盖。磁轭材料25B下沉到写字线20B的顶面之下。在TMR元件23的正上方，布置有数据选择线（读/写位线）24。数据选择线24在与X方向交叉的Y方向上延伸。数据选择线24的顶面被具有高磁导率的磁轭材料27覆盖。版权所有（C）2004，JPO

94. 发明专利

JP2003249073A MAGNETIC RANDOM ACCESS MEMORY 审中-公开
公开(公告)号：JP2003249073A
公开(公告)日：2003-09-05
申请号：JP2002158603
申请日：2002-05-31
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a MRAM having cell array structure being suitable for high integration of a cell. SOLUTION: A read block BK11 is constituted of a plurality of TMR elements 12 laminated in the longitudinal direction. One end of the TMR elements 12 in the read block BK11 is connected to a source line SL1 through a read selection switch RSW. The source line SL1 is extended in the direction of Y and connected to a ground point through a column selection switch 29C. The other end of the TMR element 12 is connected respectively and independently to read/write bit lines BL1, BL2, BL3, BL4. The read/write bit lines BL1, BL2, BL3, BL4 are extended in the direction of Y, and connected to a read circuit 29 through the column selection switch 29C. COPYRIGHT: (C)2003,JPO

95. 发明专利

JP2003209226A MAGNETIC MEMORY 审中-公开
公开(公告)号：JP2003209226A
公开(公告)日：2003-07-25
申请号：JP2002007877
申请日：2002-01-16
申请人： TOSHIBA CORP
发明人： SAITO YOSHIAKI , KISHI TATSUYA , AMANO MINORU , TAKAHASHI SHIGEKI , UEDA TOMOMASA , NISHIYAMA KATSUYA , YODA HIROAKI , ASAO YOSHIAKI , IWATA YOSHIHISA
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide a magnetic memory with which, when a coating layer made of a magnetic material is provided around write wiring, a current magnetic field can be efficiently applied to a recording layer by controlling its magnetized state. SOLUTION: This magnetic memory includes a magnetic resistance effect element (C) having a magnetic recording layer and first wiring (BL, WL) extending above or below the magnetic resistance effect element in a first direction, and records data by changing magnetization of the magnetic recording layer in a predetermined direction by a magnetic field formed by allowing a current to flow in the first wiring. The first wiring has a coating layer (SM) composed of a magnet at least on one of its two side faces. The coating layer has uniaxial anisotropy (M), with which magnetization along a longitudinal direction of the first wiring is made easy. COPYRIGHT: (C)2003,JPO

96. 发明专利

JP2003209225A MAGNETIC STORAGE DEVICE 审中-公开
公开(公告)号：JP2003209225A
公开(公告)日：2003-07-25
申请号：JP2002007601
申请日：2002-01-16
申请人： TOSHIBA CORP
发明人： UEDA TOMOMASA , TAKAHASHI SHIGEKI , AMANO MINORU , KISHI TATSUYA , SAITO YOSHIAKI , NISHIYAMA KATSUYA , YODA HIROAKI , ASAO YOSHIAKI , IWATA YOSHIHISA
IPC分类号： G11C11/14 , G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08
摘要： PROBLEM TO BE SOLVED: To provide high density memory cells by reducing the current when writing. SOLUTION: The magnetic storage device comprises a memory cell array where memory cells each having a magnetoresistive effect element 32 and an electrode 30 being connected electrically with one end of the magnetoresistive effect element are arranged in matrix, a write word line 20 being selected when information is written in the magnetoresistive effect element in the memory cell and fed with a predetermined current, a bit line 36 being connected electrically with the other end of the magnetoresistive effect element, selected when information is written in or read out from the magnetoresistive effect element and fed with a specified current, respectively, a first insulation film 24 for insulating the electrode 30 and the write word line 20 electrically, and a second insulation film 28 for insulating the electrode 30 and the bit line 36 electrically, wherein thermal conductivity of the first insulation film is set higher than that of the second insulation film. COPYRIGHT: (C)2003,JPO

97. 发明专利

JP2003030980A Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：JP2003030980A
公开(公告)日：2003-01-31
申请号：JP2001214237
申请日：2001-07-13
申请人： Toshiba Corp , 株式会社東芝
发明人： IWATA YOSHIHISA
IPC分类号： G11C11/36 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory, using an NDR element, in which data destruction in a non-selection cell at write-in is prevented. SOLUTION: Memory cells, consisting of a thyristor TH with an MIS gate and an MISFET-Q are arranged in a matrix form. A gate of the MISFET-Q and a MIS gate of the thyristor TH are connected to word lines WL1, WL2, and a drain of the MISFET-Q is connected to the bit line BL. An anode terminal of the thyristor TH is connected to a bias voltage control line REF, forming a pair with the word lines WL1, WL2 and is arranged in parallel to the word lines. Common control voltage is given to the bias voltage control line REF at standby and read-out of data, but different control voltage are given, according to the pair of word lines WL1, WL2 at write-in of data.
摘要翻译：要解决的问题：提供一种半导体存储器，其使用NDR元件，其中防止在写入期间非选择单元中的数据破坏。解决方案：由具有MIS栅极的晶闸管TH和MISFET-Q组成的存储单元以矩阵形式布置。 MISFET-Q的栅极和晶闸管TH的MIS栅极连接到字线WL1，WL2，并且MISFET-Q的漏极连接到位线BL。晶闸管TH的阳极端子连接到偏置电压控制线REF，与字线WL1，WL2形成一对，并且与字线平行布置。在待机和读出数据时，向偏置电压控制线REF提供公共控制电压，但是在写入数据时根据字线对WL1，WL2给出不同的控制电压。

98. 发明专利

JP2002343886A SEMICONDUCTOR MEMORY DEVICE 审中-公开
公开(公告)号：JP2002343886A
公开(公告)日：2002-11-29
申请号：JP2001371802
申请日：2001-12-05
申请人： TOSHIBA CORP
发明人： HORIGUCHI FUMIO , OSAWA TAKASHI , YAMADA TAKASHI , IWATA YOSHIHISA
IPC分类号： G11C11/404 , G11C11/407 , H01L21/8242 , H01L27/108 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device realizing dynamic memory by the memory cell of simple transistor structure. SOLUTION: Each MIS transistor of the semiconductor memory device is provided with a semiconductor layer 12, a source area 15 formed at the semiconductor layer 12, a drain area 14 which is formed separately from the source area 15 on the semiconductor layer 12 and where the semiconductor layer between the source area 15 and the drain area becomes a channel body in a floating state, a first gate 13 for forming a channel at the channel body, a second gate 20 for controlling the potential of the channel body by capacity connection, and a high density area 21 formed on the second gate side of the channel body and having impurity density higher than that of the channel body.

99. 发明专利

JP2002164771A DELAY COMPENSATION CIRCUIT 失效
公开(公告)号：JP2002164771A
公开(公告)日：2002-06-07
申请号：JP2000357981
申请日：2000-11-24
申请人： TOSHIBA CORP
发明人： IWATA YOSHIHISA
IPC分类号： G06F1/10 , G11C11/407 , G11C11/4076 , H03K5/00 , H03K5/131 , H03K5/14
摘要： PROBLEM TO BE SOLVED: To make a minimum unit in which phase matching can be realized small by a delay compensation circuit. SOLUTION: This delay compensation circuit is provided with a clock synchronization delay control circuit 10 which has first and second delay lines 23 and 24 composed of a plurality of delay cells 20 having the same configuration and generates a second clock signal whose phase is matched to that of a first clock signal by evaluating delay quantity to be corrected in the first delay line and deciding the number of steps of the delay cells of the second delay line so as to reflect the evaluated delay quantity on the second delay line, and a phase interpolation circuit 11 for generating the second clock signal by mixing the phases of at least two outputs among outputs of the delay cells of the decided number of steps of the second delay line and among outputs that go through the delay cells of the number of steps which is more or less than the decided number of steps.

100. 发明专利

JP2001266583A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2001266583A
公开(公告)日：2001-09-28
申请号：JP2001029460
申请日：2001-02-06
申请人： TOSHIBA CORP
发明人： TANAKA TOMOHARU , MOMOTOMI MASAKI , KATO HIDEO , NAKAI HIROTO , TANAKA YOSHIYUKI , SHIRATA RIICHIRO , ARITOME SEIICHI , ITO YASUO , IWATA YOSHIHISA , NAKAMURA HIROSHI , OHIRA HIDEKO , OKAMOTO YUTAKA , ASANO MASAMICHI , TOKUSHIGE KAORU
IPC分类号： G11C16/06 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/12 , G11C29/44 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To shorten the time required for program-verification and erase- verification and to prevent over-variation of threshold voltage even if rewrite and reerase are performed. SOLUTION: This device is provided with a memory cell array which is arranged in a matrix state and in which memory cells having electric charges accumulating layers forms a matrix, a plurality of word lines connected commonly to the memory cells forming respective rows, a plurality of bit lines connected commonly to the memory cells forming respective columns, a means for selecting a word line and applying write voltage, and a plurality of data storage circuits which store control data of a first logic level or a second logic level deciding whether write control voltage for accumulating electric charges in the electric charge accumulating layers of the memory cells connected to the selected word line is to be applied to the bit line and which is arranged in respective bit lines. The control data of the second logic level deciding that the write control voltage is not applied to the bit line is stored in a data storage circuit other than the data storage circuit in which externally inputted control data are stored.

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