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91. 发明专利

JPS63262938A FAST SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JPS63262938A
公开(公告)日：1988-10-31
申请号：JP9773187
申请日：1987-04-20
申请人： FUJITSU LTD
发明人： TAKEDA SATOSHI , TAKEO HIROSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI , MIURA NORIHISA
IPC分类号： H04J3/06 , H04L7/08 , H04L13/10 , H04L25/40
摘要： PURPOSE:To secure a system which takes out output data in a form of parallel signal and aligns the phase of the parallel signal to be outputted, that is, TSSI (Time Slot Sequence Integrity), by delaying an inputted serial digital signal by a prescribed number of bits by a variable length shift register provided at the front step of a serial-parallel conversion circuit. CONSTITUTION:A frame synchronization pattern is detected from either plural frame synchronization pattern detection circuits (300-1-300-n) provided in parallel, and the position of the pattern at parallel arrangement is detected by a synchronizing position detecting means 600. Corresponding to the above, a control signal which delays an input signal so as to set a frame synchronizing signal at the beginning of the parallel arrangement is added on a signal delay means 500, and the signal delay means 500 delays the input signal by the number of bits decided by the control signal. In such a way, the frame synchronizing signal is set at the forefront of the parallel output of the serial-parallel conversion circuit 200, and no mixing of the data of a preceding and a succeeding frames can be prevented from occurring, and also, the TSSI can be secured.

92. 发明专利

JPS6342973B2 失效
公开(公告)号：JPS6342973B2
公开(公告)日：1988-08-26
申请号：JP15509681
申请日：1981-09-30
申请人： FUJITSU LTD
发明人： TAKEO HIROSHI , MIZUSHIMA KOJI , OOHATA MICHINOBU , UECHI OSAMU
IPC分类号： H03M7/00 , H03M5/04 , H04L25/49

93. 发明专利

JPS63160438A METHOD AND APPARATUS FOR TIME DIVISION MULTIPLEX FOR BSI 失效
公开(公告)号：JPS63160438A
公开(公告)日：1988-07-04
申请号：JP31263586
申请日：1986-12-24
申请人： FUJITSU LTD
发明人： IGUCHI KAZUO , SOEJIMA TETSUO , MURANO KAZUO , OHATA MICHINOBU , TAKEO HIROSHI
IPC分类号： H04J3/00
摘要： PURPOSE:To preserve the BSI processing of a basic BSI processing PCM signal in a BSI processing multiplex PCM signal by applying BSI processing to form a basic PCM signal at each prescribed block of each incoming channel PCM signal at a basic PCM speed and multiplexing in the unit of BSI block. CONSTITUTION:The input PCM signal (i) is subject to bit serial BSI PCM signal while the BSI processing (e.g., the 8th bit is inverted and added) is applied at each block (e.g., 8-bit) in basic BSI (Bit Sequence Independence) processing circuits 201-20N. The BSI processing PCM signal is generated in the basic BSI processing circuit 201 at each input PCM signal (each channel). The BSI processing PCM signal corresponding to each channel is multiplexed in a multiplexing circuit 24 in the unit of BSI processing block, that is, in the unit of 9-bits and the result is outputted to a transmission circuit 26 as the multiplex PCM signal. Thus, the BSI processing applied at the speed of the basic PCM signal takes over as it is even in the BSI processing multiplex PCM signal.

94. 发明专利

JPS6370633A SYNCHRONIZING PATTERN DETECTOR 失效
公开(公告)号：JPS6370633A
公开(公告)日：1988-03-30
申请号：JP21645586
申请日：1986-09-12
申请人： FUJITSU LTD
发明人： TAKEO HIROSHI , OHATA MICHINOBU , TAKEDA SATOSHI , YAMAZAKI HIROSHI
IPC分类号： H04L7/08
摘要： PURPOSE:To reduce power consumption and to facilitate the constitution of circuits by providing a serial/parallel conversion circuit converting a serial digital signal into a parallel signal by bits each and a frame synchronizing pattern detection circuit applying multi-point detection. CONSTITUTION:A serial digital signal from a transmission line 1 is inputted to a shift register 21 of a serial/parallel conversion circuit 2, the register 21 converts the input signal into p-bit (p=8) parallel signals Q1-Q8, which are outputted to a register 22. A 7th bit signal is outputted from an output section R1 of the register 22, a 6th bit signal is from an output section R2, and signals are outputted similarly from output sections R3-R8. Each 1-bit output from the output sections R1-R8 is inputted to frame synchronizing pattern detection circuits 3-8-3-1 and each circuit is operatable at a low-signal speed 1/8 of that of a serial digital signal. Then multi-point detection of a synchronizing pulse of consecutive 8 frames is applied. Thus, the circuits 3-1-3-8 are constituted by low-speed circuit elements, the power consumption is reduced and the circuit constitution is facilitated.

95. 发明专利

JPS62110322A SAMPLE-AND-HOLD SYSTEM 失效
公开(公告)号：JPS62110322A
公开(公告)日：1987-05-21
申请号：JP25025485
申请日：1985-11-08
申请人： FUJITSU LTD
发明人： TAKEDA SATOSHI , OHATA MICHINOBU , TAKEO HIROSHI , NAKADE HIROSHI , YAMAZAKI HIROSHI
IPC分类号： H03M1/12
摘要： PURPOSE:To double the cycle time for one sample-and-hold and to attain analog/ digital conversion with high speed and good stability by providing two sample- and-hold circuits to one A/D converter and using the two sample-and-hold circuits while being switched in time division. CONSTITUTION:An analog signal is inputted to the sample-and-hold circuit, the signal is traced by sampling and the input signal is subjected to holding. In the constitution shown in figure, the two sample-and-hold circuits No.1, No.2 are provided and the two circuits are used while being switched in time division. Since the two sample-and-hold circuits are used in time division, the sufficient sampling time is obtained and the sampling period is quickened as fast as two times of a conventional period.

96. 发明专利

JPS60250574A CONNECTOR FOR TESTING PRINTED BOARD 失效
公开(公告)号：JPS60250574A
公开(公告)日：1985-12-11
申请号：JP10651984
申请日：1984-05-28
申请人： FUJITSU LTD
发明人： OGISO MASAAKI , TAKEO HIROSHI , TAKEDA SATOSHI , NARA KOUICHI

97. 发明专利

JPS60118025A RUSH CURRENT PREVENTING METHOD 失效
公开(公告)号：JPS60118025A
公开(公告)日：1985-06-25
申请号：JP22568583
申请日：1983-11-30
申请人： FUJITSU LTD
发明人： OOHATA MICHINOBU , KAJIWARA MASANORI , TAKEO HIROSHI , NAKADE HIROSHI
IPC分类号： H02H9/02 , H02J1/00 , H05K7/14 , H05K7/18

98. 发明专利

JPS6077219A CLOCK GENERATING CIRCUIT 失效
公开(公告)号：JPS6077219A
公开(公告)日：1985-05-01
申请号：JP18613783
申请日：1983-10-05
申请人： FUJITSU LTD
发明人： TAKEO HIROSHI , OGISO MASAAKI , NAKADE HIROSHI
IPC分类号： G06F1/04 , G06F1/06
摘要： PURPOSE:To obtain an economical clock generating circuit simplified in its circuit constitution by generating clocks with optional phases from one kind of clocks under control by a phase setting signal generator. CONSTITUTION:Clocks inputted to an input terminal 6 are inputted to the 1st counter 7 and successively counted up. The counter 7 counts up the clocks 0- 255 times and outputs the counted value to a coincidence detecting circuit 8. The circuit 8 compares the output of the counter 7 with that of the 2nd counter 9 having a phase set up by a phase setting signal generator 10, and when both outputs coincide with each other, writes its output in the 3rd counter 11 as the initializing signal of the counter 11. The counter 11 counts up clocks inputted from the terminal 6 0-255 times similarly to the counter 7 and outputs its counted value to an output terminal 12. When the output of the circuit 8 is inputted to the counter 11, the counter 11 is initialized.

99. 发明专利

JPS59214360A Detecting circuit of signal input break 失效
标题翻译：检测信号输入断路
公开(公告)号：JPS59214360A
公开(公告)日：1984-12-04
申请号：JP8791983
申请日：1983-05-19
申请人： Fujitsu Ltd
发明人： TAKEO HIROSHI , OOHATA MICHINOBU , TAKEDA SATOSHI , NAKADE HIROSHI , OGISO MASAAKI
IPC分类号： H04L25/02 , H04J3/14 , H04L1/20 , H04L13/18 , H04J3/00
CPC分类号： H04L1/20
摘要： PURPOSE:To detect the state of an input break correctly even when a clock signal extracting circuit states self-oscillation by usilizing a flip-flop circuit which inputs a receive input unipolar pulse signal and extracted from the receive signal. CONSTITUTION:When the signal input is normal, the unipolar signal 7 of the receive input is applied to an input terminal D of the flip-flop circuit 1 and the clock signal 9 extracted by the clock extracting circuit 2 is applied to an input terminal CLK, so that the input signal 7 is outputted as an output signal 10 from a terminal Q between one rise of the clock signal 9 applied to the terminal CLK to the ther rise. Some of it is branched to drive a time constant circuit 3. When, however, the signal input 7 is cut off, no signal input appears at the terminal D, so the outpt 10 from a terminal Q of the flip-flop circuit stops even if the clock signal extracting circuit 2 starts self-oscillation to generate the same signal as the clock signal at the terminal CLK. Therefore, the time constant circuit 3 does not operate and sends a signal input break detection signal 8.
摘要翻译：目的：即使当时钟信号提取电路通过使用输入接收输入单极性脉冲信号并从接收信号提取的触发器电路来说明自振荡时，也能正确地检测输入断线的状态。构成：当信号输入正常时，接收输入的单极性信号7被施加到触发器电路1的输入端D，并且由时钟提取电路2提取的时钟信号9被施加到输入端CLK ，使得输入信号7作为输出信号10从施加到端子CLK的时钟信号9的一个上升之间的端子Q输出到其上升。其中一些被分支以驱动时间常数电路3.然而，当信号输入7被切断时，在端子D处不出现信号输入，因此来自触发器电路的端子Q的输出端10甚至停止如果时钟信号提取电路2开始自振荡以产生与端子CLK处的时钟信号相同的信号。因此，时间常数电路3不工作，并发送信号输入断点检测信号8。

100. 发明专利

JPS59211316A Interface circuit 失效
标题翻译：接口电路
公开(公告)号：JPS59211316A
公开(公告)日：1984-11-30
申请号：JP8533983
申请日：1983-05-16
申请人： Fujitsu Ltd
发明人： OOHATA MICHINOBU , KAJIWARA MASANORI , TAKEDA SATOSHI , NAKADE HIROSHI , TAKEO HIROSHI
IPC分类号： H04L25/03 , H03K12/00 , H03K17/22
CPC分类号： H03K12/00
摘要： PURPOSE:To prevent malfunction due to noise at input interruption and also to attain freely the setting of duty by using two comparators and a flip-flop. CONSTITUTION:An input sinusoidal wave is inputted to the two comparators COMP1, COMP2 via a transformer Tr. The threshold level of the comparator COMP1 is V1 and that of the COMP2 is V2. An output of both comparators is inputted respectively to the flip-flop FF. Then, even if the threshold level of the comparators is set to a considerably high level, the duty is not deteriorated.
摘要翻译：目的：为了防止由于输入中断引起的噪声导致的故障，并且还可以通过使用两个比较器和一个触发器来自由地设置占空比。构成：输入正弦波通过变压器Tr输入到两个比较器COMP1，COMP2。比较器COMP1的阈值电平为V1，COMP2的阈值电平为V2。两个比较器的输出分别输入到触发器FF。然后，即使将比较器的阈值电平设定为相当高的电平，也不会降低占空比。

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