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91. 发明专利

JP2006278532A Heat treatment method and method of manufacturing semiconductor device 审中-公开
标题翻译：热处理方法及制造半导体器件的方法
公开(公告)号：JP2006278532A
公开(公告)日：2006-10-12
申请号：JP2005092751
申请日：2005-03-28
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO TAKAYUKI , MATSUO KOJI , TAMAOKI NAOKI , MOTOMIYA YOSHINORI , SUGURO KYOICHI
IPC分类号： H01L21/265 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L21/324 , H01L21/268 , H01L21/823814 , H01L29/6653 , H01L29/6659 , H01L29/7833
摘要： PROBLEM TO BE SOLVED: To provide a heat treatment apparatus capable of heat treatment while restraining any crystal defect.
SOLUTION: A translucent film 14 with a smaller refractive index than a semiconductor substrate 1 is formed on the semiconductor substrate 1. The semiconductor substrate 1 is heated to a temperature of ≥300°C and ≤600°C, and the surface of the semiconductor substrate 1 is irradiated with light having a pulse width of 0.1 msec to 100 msec through the translucent film 14. The thickness of the translucent film 14 is defined by a peak wavelength of the light and the refractive index of the translucent film 14.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够在抑制任何晶体缺陷的同时进行热处理的热处理装置。解决方案：在半导体衬底1上形成具有比半导体衬底1更小的折射率的半透明膜14.将半导体衬底1加热到≥300℃和≤600℃的温度，通过透光性膜14照射脉冲宽度为0.1毫秒〜100毫秒的光。透光性膜14的厚度由光的峰值波长和半透明膜14的折射率构成。版权所有（C）2007，JPO＆INPIT

92. 发明专利

JP2006253029A Ion implanting device and ion implanting method 审中-公开
标题翻译：离子植入装置和离子植入方法
公开(公告)号：JP2006253029A
公开(公告)日：2006-09-21
申请号：JP2005069792
申请日：2005-03-11
申请人： Toshiba Corp , 株式会社東芝
发明人： AKUTSU HARUKO , RIKIMARU KATSUMI , SUGURO KYOICHI , KAWASE YOSHIMASA
IPC分类号： H01J37/317 , H01L21/265
摘要： PROBLEM TO BE SOLVED: To provide an ion implanting device suppressing variation of angles in a wafer surface at which a wafer is irradiated with an ion beam, and an ion implanting method.
SOLUTION: This ion implanting device is equipped with a rotary disc 50 having a mounting part 51 for mounting wafers W1-W 8 and an angle adjusting mechanism 53 to adjust a cone angle θc made by a support part 52 for mounting the mounting part 51 and the support part 52, a detector 40 to detect a tilt angle θt made by the traveling direction of the ion beam 100 irradiating the wafers W1-W8 and the normal direction 200 of the wafers W1-W8, and an angle control device 70 to control the angle adjusting mechanism 53 based on the tilt angle θt.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种离子注入装置，其抑制用离子束照射晶片的晶片表面中的角度的变化，以及离子注入方法。解决方案：该离子注入装置配备有旋转盘50，旋转盘50具有用于安装晶片W1-W8的安装部51和角度调节机构53，以调节由支撑部52构成的锥角θc，以安装安装部分51和支撑部分52，检测由照射晶片W1-W8的晶片W1-W8和晶片W1-W8的法线方向200的离子束100的行进方向所产生的倾斜角θt的检测器40以及角度控制装置 70，以根据倾斜角度θt来控制角度调节机构53。版权所有（C）2006，JPO＆NCIPI

93. 发明专利

JP2006005373A Manufacturing method for semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006005373A
公开(公告)日：2006-01-05
申请号：JP2005217569
申请日：2005-07-27
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO TAKAYUKI , IINUMA TOSHIHIKO , SUGURO KYOICHI
IPC分类号： H01L21/265 , H01L21/28 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor device which can accurately control the profile of impurities.
SOLUTION: The method for manufacturing the semiconductor device comprises a step of implanting ion of an impurity element in a semiconductor region 1; a step of implanting the ions of the element having the same conductivity as group IV element or the impurity element, and of mass number larger than that of the impurity element as a predetermined element in the semiconductor region; a step of forming a crystal defect region 5 of an amorphous state, a step of illuminating and annealing the region where the impurity element and the predetermined element are injected, with light of flash lamp, to recover a crystal defect of the crystal defect region of the amorphous state and activate the impurity element, wherein an annealing step, by illuminating the light of the flash lamp is performed in a preheated state of the semiconductor region at a temperature, capable of maintaining the amorphous state of the crystal defect region.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供可以精确地控制杂质的形状的半导体装置的制造方法。解决方案：用于制造半导体器件的方法包括：在半导体区域1中注入杂质元素的离子的步骤; 将具有与IV族元素或杂质元素相同的导电性的元素的离子和质量数大于杂质元素的离子的元素作为预定元素注入到半导体区域中的步骤; 形成非晶状态的晶体缺陷区域5的步骤，利用闪光灯照射退火杂质元素和预定元素的区域的步骤，以回收晶体缺陷区域的晶体缺陷非晶状态并激活杂质元素，其中通过照射闪光灯的退火步骤在能够保持晶体缺陷区域的非晶状态的温度下在半导体区域的预热状态下进行。版权所有（C）2006，JPO＆NCIPI

94. 发明专利

JP2005033137A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005033137A
公开(公告)日：2005-02-03
申请号：JP2003273603
申请日：2003-07-11
申请人： Toshiba Corp , 株式会社東芝
发明人： IINUMA TOSHIHIKO , MIZUSHIMA ICHIRO , DEWA MITSUAKI , MIYANO KIYOTAKA , SUGURO KYOICHI
IPC分类号： H01L21/28 , H01L21/336 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66477 , H01L29/165 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/66628
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with a lower parasitic resistance while reducing the occurrence of a leak on a junction and a faulty gate insulating film.
SOLUTION: The semiconductor device comprises a semiconductor substrate (41), element separation/insulation areas (42) which are separately formed on the semiconductor substrate and determine an element area, a pair of impurity diffusion areas (47) which are formed in the element area so as to contact with the element separation/insulation area and have surfaces protruding from the element separation/insulation areas, SiGe films (49) which are continuously formed from the top faces of the pair of impurity diffusion areas to parts of the sides of the impurity diffusion areas and have a Ge concentration which is higher on the side of the impurity diffusion area than on a surface thereof, a metal silicide layer (54) formed on the SiGe film, and a gate electrode (44) which is formed in the element area on the semiconductor substrate via a gate insulating film (53) and has a side wall insulating film (48) on its side.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有较低寄生电阻的半导体器件，同时减少结和漏极栅极绝缘膜上的泄漏的发生。解决方案：半导体器件包括半导体衬底（41），元件分离/绝缘区域（42），其分开形成在半导体衬底上并确定元件区域，形成一对杂质扩散区域（47）在元件区域中与元件分离/绝缘区域接触并且具有从元件分离/绝缘区域突出的表面，从一对杂质扩散区域的顶面连续形成的SiGe膜（49）杂质扩散区域的侧面，并且具有在杂质扩散区域侧比在其表面上高的Ge浓度，形成在SiGe膜上的金属硅化物层（54）和栅极电极（44），经由栅极绝缘膜（53）形成在半导体基板的元件区域中，并且在侧面具有侧壁绝缘膜（48）。版权所有（C）2005，JPO＆NCIPI

95. 发明专利

JP2005032998A Method and device for heat-treating semiconductor substrate 有权
标题翻译：用于热处理半导体基板的方法和装置
公开(公告)号：JP2005032998A
公开(公告)日：2005-02-03
申请号：JP2003196556
申请日：2003-07-14
申请人： Toshiba Corp , 株式会社東芝
发明人： TATSUTA SHINICHI , NISHIOKA TAKESHI , HIRONO MASATOSHI , SUGURO KYOICHI , ITO TAKAYUKI
IPC分类号： H01L21/265
摘要： PROBLEM TO BE SOLVED: To provide a method for heat-treating a semiconductor substrate capable of satisfactorily activating an impurity diffusion layer without causing temperature unevenness or a hot spot on the semiconductor substrate, and to provide a heat treatment device.
SOLUTION: The method for heat-treating the semiconductor device by the use of the light source 100 for activating impurity injected in the semiconductor substrate 205 comprises a step of forming a light absorbing film 250 comprising a material having a refractive index n-ik with its real part n of 0.5 to 2.2 and its imaginary part k of not more than 1.0, and absorbing light energy from the light source and converting the light energy into heat energy; and a step of heat treating to activate the impurity by radiating the light energy from the light source to the light absorbing film.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够令人满意地激活杂质扩散层的半导体衬底的热处理而不引起半导体衬底上的温度不均匀或热点，并提供一种热处理器件。解决方案：通过使用用于激活在半导体衬底205中注入的杂质的光源100对半导体器件进行热处理的方法包括形成光吸收膜250的步骤，该光吸收膜250包括折射率为n- ik的实部n为0.5〜2.2，虚部k为1.0以下，吸收来自光源的光能，将光能转换成热能; 以及通过将来自光源的光能辐射到光吸收膜来热处理以激活杂质的步骤。版权所有（C）2005，JPO＆NCIPI

96. 发明专利

JP2005019650A Processor, manufacturing apparatus, processing method, and method of manufacturing electronic device 有权
标题翻译：处理器，制造装置，处理方法和制造电子器件的方法
公开(公告)号：JP2005019650A
公开(公告)日：2005-01-20
申请号：JP2003181731
申请日：2003-06-25
申请人： Toshiba Corp , 株式会社東芝
发明人： SUGURO KYOICHI , ITANI KOJI , ITO TAKAYUKI
IPC分类号： H01L21/31 , H01L21/00 , H01L21/02 , H01L21/28 , H01L21/306 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/32 , H01L21/8234 , H01L27/088 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28185 , H01L21/02046 , H01L21/28202 , H01L21/28211 , H01L21/28238 , H01L21/3144 , H01L21/32 , H01L21/67115 , H01L21/67155 , H01L21/823462 , H01L29/513 , H01L29/518
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing apparatus capable of forming an ultra-thin insulating film having superior electric characteristics. SOLUTION: The manufacturing apparatus is provided with a processing chamber 11 for performing processing for a substrate 1; a susceptor 12 which has a surface made of a quartz and is disposed in the processing chamber 11, and is provided with a heating source 13 for heating the placed substrate 1 at 650°C or below; an introducing system 38 for supplying at least any one of an oxide gas, a nitride gas, a reducing gas, or a gas containing halogen substantially in parallel with the substrate 1; a transparent window 15 disposed on the upper part of the processing chamber 11 oppositely to the susceptor 12; and a light source 36 having plurality of light-emitting wavelengths for irradiating the surface of the substrate 1 with light from the transparent window 15 like a pulse of a pulse width of 0.1 m/s-200 m/s. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够形成具有优异电特性的超薄绝缘膜的制造装置。解决方案：制造装置设置有用于对基板1进行处理的处理室11; 具有由石英制成的表面并设置在处理室11中的基座12，并且设置有用于在650℃以下加热被放置的基板1的加热源13; 引入系统38，用于供应氧化物气体，氮化物气体，还原气体或含有基本上与衬底1平行的卤素的气体中的至少一种; 设置在处理室11的与感受器12相对的上部的透明窗口15; 以及具有多个发光波长的光源36，如同脉冲宽度为0.1m / s-200m / s的脉冲，用于从透明窗15照射基板1的表面。版权所有（C）2005，JPO＆NCIPI

97. 发明专利

JP2004311585A Method of manufacturing semiconductor device 有权
公开(公告)号：JP2004311585A
公开(公告)日：2004-11-04
申请号：JP2003100612
申请日：2003-04-03
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO TAKAYUKI , SUGURO KYOICHI
IPC分类号： H01L27/092 , H01L21/265 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/823842
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having a low resistance and shallow impurity diffusion region and being provided with an satisfactory driving force.
SOLUTION: An insulating gate including at least a gate insulating film and a gate electrode doped with n-type impurities is formed on a single crystal semiconductor substrate, impurity ions are selectively implanted into the surface layer of the semiconductor substrate adjacent to the insulating gate and the gate electrode. First thermal processing at a first substrate temperature is performed to diffuse the impurity ions implanted into the gate electrode, and suppress the diffusion of the impurity ions implanted into the surface layer of the semiconductor substrate. After that, thermal processing of a processing period shorter than that of the first thermal processing at a second substrate temperature higher than the first substrate temperature is performed to activate the impurity ions implanted into the surface layer of the semiconductor substrate.
COPYRIGHT: (C)2005,JPO&NCIPI

98. 发明专利

JP2004207562A Process for fabricating semiconductor device and system for producing semiconductor 有权
公开(公告)号：JP2004207562A
公开(公告)日：2004-07-22
申请号：JP2002375979
申请日：2002-12-26
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA TAKESHI , MISAWA HISATOKU , SUGURO KYOICHI
IPC分类号： G03F7/20 , H01L21/02 , H01L21/027 , H01L21/266
CPC分类号： H01L21/266
摘要： PROBLEM TO BE SOLVED: To provide a process for fabricating a semiconductor device which reduces the possibility that a semiconductor element breaks down with residual charges on a substrate being processed in a process for producing a semiconductor using a stencil mask.
SOLUTION: The process for fabricating a semiconductor device comprises a step for irradiating a substrate 12 being processed with charged particles 13 through a stencil mask 11 having an opening disposed oppositely to the substrate 12 being processed, wherein the potential difference between the stencil mask 11 and the substrate 12 being processed is regulated depending on the level of a current flowing between the substrate 12 being processed and the ground.
COPYRIGHT: (C)2004,JPO&NCIPI

99. 发明专利

JP2004207561A Process for fabricating semiconductor device and system for producing semiconductor 审中-公开
标题翻译：制造半导体器件的方法和用于生产半导体的系统
公开(公告)号：JP2004207561A
公开(公告)日：2004-07-22
申请号：JP2002375978
申请日：2002-12-26
申请人： Toshiba Corp , 株式会社東芝
发明人： SHIBATA TAKESHI , SUGURO KYOICHI
IPC分类号： G03F7/20 , H01L21/027
CPC分类号： G03F1/20 , G03F7/70066 , G03F7/70983 , H01J2237/31794 , Y10S430/143
摘要： PROBLEM TO BE SOLVED: To provide a system for producing a semiconductor in which deterioration, e.g. deformation or damage, of a stencil mask being employed in a semiconductor production process is suppressed.
SOLUTION: In the system for producing a semiconductor, a stencil mask 10 having a thin film part 12 and a part 15 for supporting the thin film part 12 is irradiated with a particle beam 16 and a substrate to be processed is irradiated with the particle beam 16 through an opening 17 formed at the thin film part 12 of the stencil mask 10. In the process for fabricating a semiconductor device, the stencil mask 10 is irradiated with the particle beam 16 while adjusting the irradiation area of the particle beam 16 such that the end part of the irradiation area does not exist on the thin film part 12 of the stencil mask 10.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种制造半导体的系统，其中劣化例如抑制在半导体制造工序中使用的模板掩模的变形或损伤。解决方案：在用于制造半导体的系统中，用粒子束16照射具有薄膜部分12的模板掩模10和用于支撑薄膜部分12的部分15，并且将被处理基板照射粒子束16通过形成在模板掩模10的薄膜部分12处的开口17.在制造半导体器件的过程中，模板掩模10被照射粒子束16，同时调节粒子束的照射面积 16，使得在模板掩模10的薄膜部分12上不存在照射区域的端部。（C）2004年，JPO＆NCIPI

100. 发明专利

JP2003115277A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003115277A
公开(公告)日：2003-04-18
申请号：JP2001307607
申请日：2001-10-03
申请人： TOSHIBA CORP
发明人： MURAKOSHI ATSUSHI , SUGURO KYOICHI
IPC分类号： C23C14/48 , H01J37/317 , H01L21/265
摘要： PROBLEM TO BE SOLVED: To realize acceleration-deceleration type ion implantation in which shallow p-n junctions can be easily formed. SOLUTION: B ions are accelerated to initial acceleration energy by an extraction electrode 2, and the B ions are decelerated to final acceleration energy by a post-acceleration tube 4, where they are set as: 1

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