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91. 发明专利

JPS6238645A DEMODULATOR 失效
公开(公告)号：JPS6238645A
公开(公告)日：1987-02-19
申请号：JP17767985
申请日：1985-08-14
申请人： FUJITSU LTD
发明人： YAGI TAKESHI , TAKENAKA SADAO , FUKUDA EISUKE
IPC分类号： H04L7/027 , H04L7/02 , H04L27/00 , H04L27/38
摘要： PURPOSE:To optimize always the clock phase to the phase of a base band signal by providing a phase control circuit between an identification device and a variable phase shifter, inputting an error signal of the identifying deice to the phase control circuit and sending a phase control signal of a clock to the base band thereby adjusting the phase shift of the variable phase shifter. CONSTITUTION:The phase control circuit 5 is provided between the identifying device 2 and the variable phase shifter 4 and generates a phase control signal advancing/retarding the clock phase based on an error signal from the identifying device 2. The phase of an input clock to the device 2 is held to an optimum value to the base band signal by using the phase control signal. Then an integration circuit 51 integrates an error signal inputted from the device 2 and outputs the DC component. An A/D converter 52 converts the DC component from the circuit 51 from an analog signal into a digital signal and inputs the result to a microprocessor. The microprocessor 53 discriminates to advance/retard the clock phase to the base band signal. A D/A converter 54 converts a digital output of the microprocessor 53 into an analog signal and inputs it to the variable phase shifter 4 as a phase control signal.

92. 发明专利

JPS61245659A GENERATOR FOR DC COMPONENT SUPPRESSION PATTERN 失效
公开(公告)号：JPS61245659A
公开(公告)日：1986-10-31
申请号：JP8772785
申请日：1985-04-24
申请人： FUJITSU LTD
发明人： MACHIDA KOICHI , FUKUDA EISUKE , TAKEDA YUKIO
IPC分类号： H04L27/36 , H04L27/00
摘要： PURPOSE:To produce a pattern where the DC component of a multi-value QAM wave is suppressed by setting the 2nd signal point at a position symmetrical to the 1st signal point centering on an axis I or Q together with the 3rd signal point set at a position symmetrical to the 2nd signal point centering on the axis Q or I and repeating these setting operations. CONSTITUTION:As shown in the figure, the signal points are produced symmetrically to 0-3 and axes I and Q. Then the signal points are produced in the same way with the base point set at a point 4 more inside from 0 by 1. These operations are repeated to produce the signal points to all signal point trains y=0 and y=7 at the most outer side. Then the signal points are produced in the same procedure for the signal point trains of y=1 and y=6. These operations are repeated for production of all 64 signal points. This procedure is repeated from 0. Thus the DC component is suppressed for the spectrum of a pattern generator which forms such arrangements of signal points. These procedures are stored in a ROM7 and then read out successively with the output given from a counter 6 to be applied to a 64-value QAM modulator via a capacitor. Thus the arrangement of signal points can be shown.

93. 发明专利

JPS61224761A CIRCUIT FOR SUPPRESSING AND INTEGRATING AND CONTROLLING LOW FREQUENCY COMPONENT 失效
公开(公告)号：JPS61224761A
公开(公告)日：1986-10-06
申请号：JP6564785
申请日：1985-03-29
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE , TAKEDA YUKIO
IPC分类号： H04L27/38 , H04L27/00
摘要： PURPOSE:To decrease the circuit scale by providing an arithmetic logic operation unit comprising an instruction decoder, an address register, an I-ch register, a Q-ch register and an arithmetic section or the like and using it in common in time-division form. CONSTITUTION:The arithmethic unit ALU 21 consists of the instruction decoder 31, the address register 32, the I-ch register 42, the Q-ch register 43 and the arithmetic section 51 or the like and makes arithmetic based on a command given via the instruction decoder 31. The result of arithmetic of the arithmetic section 51 of the unit ALU 21 is set to a register 47 via a buffer 48, and the arithmetic is performed at each frame decided by a multi-value orthogonal amplitude modulation QAM system. Then the final result is fed to a comparator circuit of the I-ch system or the Q-ch system in time division via the register 42 or 43 depending on the gate signal on a gate line 37 from the register 32. Thus, the unit ALU 21 is used in common by the I-ch and the Q-ch system of the unit ALU 21 and the circuit scale is reduced.

94. 发明专利

JPS60152156A SERVICE CHANNEL SIGNAL INSERTING SYSTEM 失效
公开(公告)号：JPS60152156A
公开(公告)日：1985-08-10
申请号：JP745484
申请日：1984-01-19
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE , TAKEDA YUKIO , TAKENAKA SADAO
IPC分类号： H04L25/49 , H04L27/34 , H04L27/36 , H04L27/38
摘要： PURPOSE:To prevent an error rate of a data from deteriorating by inserting a service channel signal to a frame slot. CONSTITUTION:Switches SW1, SW2 are connected as shown in dotted line sides at the frame slot, a signal of the CH1 is outputted at an output D0 and a signal applied with EX-OR by an EX-OR circuit 2 for signals of the CH1 and CH2 is outputted at an output D1. Then a signal EX-ORed for a signal of the CH1 and a service channel signal by an EX-OR circuit 3 is outputted at an output D2.

95. 发明专利

JPS59112748A Data transmission and reception system 失效
标题翻译：数据传输和接收系统
公开(公告)号：JPS59112748A
公开(公告)日：1984-06-29
申请号：JP21275982
申请日：1982-12-06
申请人： Fujitsu Ltd
发明人： NAKAMURA HIROSHI , FUKUDA EISUKE , SASAKI SUSUMU
IPC分类号： H04B3/04 , H04L25/49 , H04L27/34 , H04L27/36 , H04L27/38
CPC分类号： H04L27/3836 , H04L27/368
摘要： PURPOSE: To easily cope with a factor of error occurrence by constituting the level converter in a transmission system of a memory and a D/A converter, and storing the memory with a digital signal corresponding to an input signal and correction data on an error.
CONSTITUTION: In the multivalued quadrature amplitude modultion, the 1st level converters of the 1st and the 2nd channel systems on a transmission side consists of memories 111 and 121, adders 112 and 122, and D/A converters 113 and 123. The memories 111 and 121 are stored with digital data d11 and d21 corresponding to inpt signals D1 and D2, digital data for correcting an error caused by the nonlinear distortion of a high-output amplifier 136, and error correction data d12 and d22 for an error caused by the modulation distortion of mixers 115 and 125. Data obtained by adding 112 and 122 correction data d12 or d22 of the corresponding system to error correction data which exerts influence upon the other system and data d11 and d21 are converted 113 and 123 from digital to analog and transmitted. Demodulators on a reception side consist of A/D converters 213 and 223, adders 212 and 222, and memories 211 and 221 to correct errors.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过构成存储器和D / A转换器的传输系统中的电平转换器来容易地应对错误发生的因素，并且将存储器与对应于输入信号的数字信号和校正数据存储在错误上。构成：在多值正交幅度模式中，发送侧的第一和第二信道系统的第一级转换器由存储器111和121，加法器112和122以及D / A转换器113和123组成。存储器111和 121存储与数字数据d11和d21对应的信号D1和D2，用于校正由高输出放大器136的非线性失真引起的误差的数字数据和用于由调制引起的误差的纠错数据d12和d22 混合器115和125的失真。通过将相应系统的112和122校正数据d12或d22添加到对其他系统和数据d11和d21施加影响的纠错数据获得的数据被转换为113和123从数字到模拟和发送。接收侧的解调器由A / D转换器213和223，加法器212和222以及存储器211和221组成，以校正错误。

96. 发明专利

JPS5789362A AUTOMATIC ADJUSTING CIRCUIT FOR DISCRIMINATION LEVEL 失效
公开(公告)号：JPS5789362A
公开(公告)日：1982-06-03
申请号：JP16615580
申请日：1980-11-26
申请人： FUJITSU LTD
发明人： FUKUDA EISUKE
IPC分类号： H03M5/04 , H04L25/03 , H04L25/49 , H04N7/025 , H04N7/03 , H04N7/035
摘要： PURPOSE:To prevent the degradation of the discrimination error rate due to the distortion and the level fluctuation of a receiving signal, by using maximum and minimum levels of a multilevel signal as new discrimination levels to detect the level of the receiving signal and controlling plural discrimination levels. CONSTITUTION:The quad pulse train from a transmission line is inputted to comparators D1-D3 and is compared with discrimination levels T1-T3 and is outputted as two-bit parallel binary pulse trains from output terminals 5-1, and 5-2. Meanwhile, comparators A1 and A2 compare signals of level 0 and level 3 in the quad pulse train of levels 0-3 with discrimination levels TA1 and TA2 to detect an outside or inside distortion of the actual eye pattern for an ideal eye pattern. These detection outputs a1, a2, d1, and d2 are used to set an output Y of an OR gate G2 to ''1'' or ''0''.

97. 发明专利

JPS56158537A COMPENSATING METHOD FOR FREQUENCY CHARACTERISTIC 失效
公开(公告)号：JPS56158537A
公开(公告)日：1981-12-07
申请号：JP6259180
申请日：1980-05-12
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKENAKA SADAO , KURIHARA HIROSHI , FUKUDA EISUKE , YOSHIDA AKITERU
IPC分类号： H03H7/01 , H03G5/16 , H04B1/10 , H04B7/015
摘要： PURPOSE:To enable equalization to chevron type fading, by extracting a suitable signal component from a reception spectrum and changing the characteristic of a band block type resonance circuit in a transmission line with this signal automatically. CONSTITUTION:In a radio digital system, a reception input is outputted via a reception amplifier 41, variable resonance circuit 1, buffer 42, band block type variable resonance circuit 46 and an output amplifier 43. The pilot signal of the lower end P1, center P2, upper end P3 is extracted at a pilot extracting circuit 40 from the power spectrum of the reception signal of the amplifier 43 and inputted to a control circuit 2. At the circuit 2, voltages VF1, VQ relating to the values of P2-P1, P2-(P1+P3)/2 are outputted at the circuit 2 to control the circuit 1 and equalize the chevron type fading. Further, the voltages VF1, VQ are converted into voltages VF2, VD at level conversion circuits 44, 45, respectively, and this signal controls a circuit 46 and equalize the chevron type fading.

98. 发明专利

JPS56141625A AUTOMATIC COMPENSATION SYSTEM OF PROPAGATION DISTORTION 失效
公开(公告)号：JPS56141625A
公开(公告)日：1981-11-05
申请号：JP4599580
申请日：1980-04-08
申请人： FUJITSU LTD
发明人： TAKENAKA SADAO , FUKUDA EISUKE , KURIHARA HIROSHI
IPC分类号： H04B1/10 , H04B7/005
摘要： PURPOSE:To compensate a propagation distortion by controlling a variable coefficient meter and a variable pase meter, which have been connected to a feedback line of the high gain amplifier. CONSTITUTION:The feedback line which has been provided on the high gain amplifier in the compensating circuit 11 is constituted of hybrid circuits 16, 17, a delay circuit 18, a variable coefficient meter 19, a variable phase meter 20 and a subtracter 14. In accordance with a detection output of each frequency component of the primary means 12 for detecting a center frequency component of the receiving signal spectrum and the frequency component of both the sides, the control part 13 discriminates a frequency characteristic of fading and controls the variable coefficient meter 19 and the variable phase meter 20. Accordingly the receiving signal spectrum is made a prescribed spectrum and the propagation distortion is compensated automatically.

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