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    • 1. 发明专利
    • Rail-to-rail charge pump circuit
    • 铁路到铁路充电泵电路
    • JP2003309467A
    • 2003-10-31
    • JP2003099538
    • 2003-04-02
    • Northrop Grumman Corpノースロップ・グラマン・コーポレーション
    • CHU PETER F
    • H03L7/093H03F3/30H03F3/45H03L7/089
    • H03F3/3067H03F3/4508H03F3/45098H03F2203/45362H03F2203/45702H03L7/0895
    • PROBLEM TO BE SOLVED: To provide a charge pump circuit for a current source and a current sink to a loop filter. SOLUTION: This charge pump circuit 60 tunes a tank circuit 66 in response to two logic signals from a phase comparator 52 for comparing a signal of applying frequency division to a signal of a voltage-controlled oscillator with a reference signal and outputting an error signal representing phase difference. One signal from the phase comparator 52 is applied to the base terminal of a transistor 104, thereby causing a mirror current to flow to a transistor 108. The other signal from the phase comparator 52 is applied to the base terminal of a transistor 94, thereby causing a mirror current to flow to a transistor 98. A bleed resistor 114 is coupled to the base terminal of the transistor 104 so that the charge pump circuit provides a constant phase comparator gain. COPYRIGHT: (C)2004,JPO
    • 要解决的问题:为电流源和电流吸收器提供用于环路滤波器的电荷泵电路。 解决方案:该电荷泵电路60响应于来自相位比较器52的两个逻辑信号调谐电路66,用于将施加频率的信号与具有参考信号的压控振荡器的信号进行比较,并输出 表示相位差的误差信号。 来自相位比较器52的一个信号被施加到晶体管104的基极端子,从而使反射镜电流流向晶体管108.来自相位比较器52的另一个信号被施加到晶体管94的基极, 导致反射镜电流流向晶体管98.放电电阻器114耦合到晶体管104的基极端子,使得电荷泵电路提供恒定的相位比较器增益。 版权所有(C)2004,JPO
    • 2. 发明专利
    • Resetable cascadable divide-by-two circuit
    • 可复位的二分法电路
    • JP2003309466A
    • 2003-10-31
    • JP2003099555
    • 2003-04-02
    • Northrop Grumman Corpノースロップ・グラマン・コーポレーション
    • CHU PETER F
    • H03K21/00H03K23/00H03K23/50H03L7/089H03L7/183
    • H03K23/50H03L7/0895H03L7/183
    • PROBLEM TO BE SOLVED: To provide a cascadable divide-by-two binary counter circuit for use as a synchronous divider circuit in a phase lock loop.
      SOLUTION: This binary counter circuit 120 is composed of a D-FF (D flip- flop) 122 and cascaded. An AND gate 124 is responsive to an output Q from the counter circuit of the preceding stage and an output P dependent upon outputs of all of the counter circuits of the preceding stage and supplies an output to an exclusive-OR gate 126. The exclusive-OR gate 126 also receives an output of the FF 122 and supplies an exclusive-OR output to an AND gate 128. An output of the AND gate 128 is supplied to a D input of the FF 122. A reset signal to the AND gate 128 is generated by an appropriate decoder.
      COPYRIGHT: (C)2004,JPO
    • 要解决的问题:提供一种用于在锁相环中作为同步分频器电路的可级联的二分之二二进制计数器电路。

      解决方案:该二进制计数器电路120由D-FF(D触发器)122和级联组成。 与门124响应于来自前级的计数器电路的输出Q和取决于前级的所有计数器电路的输出的输出P,并将输出提供给异或门126。 或门126还接收FF 122的输出,并将异或输出提供给与门128.与门128的输出被提供给FF 122的D输入。复位信号到与门128 由适当的解码器产生。 版权所有(C)2004,JPO