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1. 发明专利

JPH0794791A CONSTRUCTION OF HIGH-TEMPERATURE SUPERCONDUCTING THIN FILM AND ITS MANUFACTURE 失效
公开(公告)号：JPH0794791A
公开(公告)日：1995-04-07
申请号：JP25628493
申请日：1993-09-21
申请人： KOKUSAI CHODENDO SANGYO GIJUTS , NEC CORP , SANYO ELECTRIC CO
发明人： YAMAGUCHI KEIICHI , ENOMOTO YOICHI , MITSUZUKA TSUTOMU , YOSHIKAWA SHUICHI
IPC分类号： C23C14/08 , H01L39/22 , H01L39/24
摘要： PURPOSE:To facilitate the control of a large current high temperature superconductive device by a method wherein the curvature radius of the step part of a substrate having a step is not less than a specific value and a high- temperature superconducting thin film is made of composition of a specific system. CONSTITUTION:A high-temperature superconducting thin film 2 is deposited on a substrate 1 having a step. A slope exists between the upper step corner 3a and the lower step corner 3b of the substrate 1. The curvature radius of the corner 3a is predetermined to be not less than 50nm. If the radius of curvature of the corner 3a is not less than 50nm, the particle boundaries of the superconducting material are avoided and the high-temperature superconducting thin film 2 suitable for a large current can be obtained. The high-temperature superconducting thin film is made of LnBa2Cu2O7-8 (wherein Ln denotes one of Y, La, Er, Eu, Gd, Dy, and Ho) or TlxBayCazCuuOv (wherein the combination of x:y:z:u:v is one of 2:2:2:3:10, 1:2:2:3:9 and 1:2:3:4:11).

2. 发明专利

JPH07122927A ARRAY ANTENNA AND ITS MANUFACTURE 失效
公开(公告)号：JPH07122927A
公开(公告)日：1995-05-12
申请号：JP26494593
申请日：1993-10-22
申请人： KOKUSAI CHODENDO SANGYO GIJUTS , NEC CORP , DU PONT
发明人： SUZUKI KATSUMI , ENOMOTO YOICHI , TANAKA SHOJI , MURPHY ARTHUR T , YAMAGUCHI KEIICHI
IPC分类号： H01L39/00 , H01L39/02 , H01P5/12 , H01P11/00 , H01Q1/24 , H01Q1/36 , H01Q13/08 , H01Q21/06 , H01Q23/00 , H03D9/06 , H04B1/26
摘要： PURPOSE: To use a superconductor feed line in a low frequency area with low loss by providing a nonlinear element inside a unit wiring pattern composed of a superconductor thin film wiring pattern for each element unit of an antenna and arranging it in an array shape. CONSTITUTION: The wiring pattern of the plural antennas 4c in a patch shape and plural oxide superconductor feed lines 4b for instance is formed on the same surface of the main surface of a substrate 1, one or plural extremely short normal conducting areas are provided on a part of the wiring pattern and the part of the wiring pattern is turned to a nonlinear response part composed of one or plural superconducting/normal conducting (SNS) junctions. Further, a thin DC bias line 4d for biasing a DC current to the nonlinear response part 4a is provided from the opposite side of the part where the antenna 4c of the patch shape is in contact with the nonlinear response part 4a. In this case, the dimension of the antenna 4c in the patch shape depends on the thickness of the substrate 1, the dielectric constant of the substrate l and a resonance frequency.

3. 发明专利

JPH0794790A SUPERCONDUCTING DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0794790A
公开(公告)日：1995-04-07
申请号：JP23396393
申请日：1993-09-21
申请人： KOKUSAI CHODENDO SANGYO GIJUTS , NEC CORP , SHARP KK
发明人： YAMAGUCHI KEIICHI , ENOMOTO YOICHI , MITSUZUKA TSUTOMU , SUZUKI KATSUMI , FUJIMOTO MANABU
IPC分类号： B82B1/00 , H01L39/22 , H01L39/24
摘要： PURPOSE:To form only one superconducting junction plane in a minute region with a good reproducibility and facilitate the manufacture of a quantum effect device which is peculiar to superconductor by the control of the surface of a substrate. CONSTITUTION:The property of superconductor that a warped superconducting thin film containing no grain boundary is obtained if the growth plane of the thin film has a curvature radius not less than a specific value is utilized to make the curvature radius of the growth plane discontinuous on the contact line between the two warped planes 2 of a substrate 4 and to form only one plane of a grain junction 6. As a growth plane forming method, FIB lithography and ion beam etching are utilized.

4. 发明专利

JP2007335554A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007335554A
公开(公告)日：2007-12-27
申请号：JP2006164314
申请日：2006-06-14
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： YAMAGUCHI KEIICHI
IPC分类号： H01L21/768 , H01L27/148
CPC分类号： H01L21/76855 , H01L21/76843 , H01L27/14806 , H01L29/76816
摘要： PROBLEM TO BE SOLVED: To prevent the deterioration of annealing effect in the annealing treatment upon the manufacture of a semiconductor device caused by that the Ti film forming the barrier metal of a contact of a tungsten plug structure traps the hydrogen produced from within the gas atmosphere or the deposited film upon the annealing.
SOLUTION: The Ti film is formed on the underside and the sidewall of the contact, and a Ti silicide film of C49 phase is formed on the underside by applying annealing treatment. After the unreacted Ti film is removed, a TiN film 82 is formed on the underside and the sidewall. The phase transition of the Ti silicide film of C49 phase to a Ti silicide film 80 of C54 phase is carried out by applying the annealing treatment again. Tungsten is deposited in the remaining space in a contact hole to form a tungsten plug 84.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题为了防止在制造半导体器件时退火处理中的退火效果的劣化，由于形成钨插塞结构的接触的阻挡金属的Ti膜捕获从内部产生的氢，气体气氛或退火时的沉积膜。解决方案：Ti膜形成在接触件的下侧和侧壁上，通过退火处理在下侧形成C49相的Ti硅化物膜。在去除未反应的Ti膜之后，在下侧和侧壁上形成TiN膜82。通过再次进行退火处理，进行C49相的Ti硅化物膜与C54相的Ti硅化物膜80的相变。钨沉积在接触孔中的剩余空间中以形成钨丝塞84.版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2006179709A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006179709A
公开(公告)日：2006-07-06
申请号：JP2004371834
申请日：2004-12-22
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： YAMAGUCHI KEIICHI
IPC分类号： H01L21/301 , H01L21/02 , H01L21/60
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To inhibit the generation of the nonconformity of a semiconductor device due to a film peeling at a cut place by a dicing, particularly at angle sections at the four corners of a semiconductor chip. SOLUTION: A manufacturing method for the semiconductor device has a process in which an supporter is bonded on a semiconductor wafer 1a with a plurality of the semiconductor chips 1 with formed first wirings 3 through an adhesive, and the process in which second wirings connected to the first wirings 3 and extended up to the rears of semiconductor chips through insulating films are formed. The manufacturing method further has the process in which protective films are formed on the second wirings, the process, in which the semiconductor wafer 1a is etched while leaving a region, in which dicing lines (boundaries S) are crossed, and the process in which the semiconductor wafer 1a is diced along the boundaries S and divided into separate semiconductor chip 1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制由于通过切割在切割位置处的膜剥离而导致的半导体器件的不整合的产生，特别是在半导体芯片的四个角的角部。解决方案：半导体器件的制造方法具有通过粘合剂将支撑体与具有形成的第一布线3的多个半导体芯片1接合在半导体晶片1a上的工序，其中第二布线连接到第一布线3并且通过绝缘膜延伸到半导体芯片的凸起。该制造方法还具有在第二配线上形成保护膜的工序，其中半导体晶片1a在切割切割线（边界S）交叉的区域被蚀刻的过程中，以及其中半导体晶片1a沿着边界S切割并分成单独的半导体芯片1.版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2006030230A Method for manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006030230A
公开(公告)日：2006-02-02
申请号：JP2004204186
申请日：2004-07-12
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： YAMADA KOJI , YAMAGUCHI KEIICHI , NOMA TAKASHI , SEKI YOSHINORI
IPC分类号： G03F7/38 , G03F7/40 , H01L21/301 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To suppress failure in patterning in a resist layer as much as possible in a method for manufacturing a chip size package type semiconductor device. SOLUTION: After an aperture 10w is formed on the back face of a semiconductor substrate 10, a second insulating film 16 and a second resist layer 17 are formed thereon. The surface of the resist layer 17 is subjected to hydrophilic treatment by ashing. Then the substrate is exposed through a mask having an aperture in a region from a part on a pad electrode 12 in the bottom to a dicing line DL. Then the substrate 10 having the second resist layer 17 is immersed in a developing solution 20d to develop the second resist layer 17. As the developing solution 20d reaches the bottom and near the bottom of the aperture 10w, the second resist layer 17 in the region from a part on the pad electrode 12 to the dicing line DL is reliably removed to reliably expose a part of the second insulating film 16. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了在芯片尺寸封装型半导体器件的制造方法中尽可能多地抑制抗蚀剂层中的图案化失败。解决方案：在半导体衬底10的背面上形成孔10w之后，在其上形成第二绝缘膜16和第二抗蚀剂层17。抗蚀剂层17的表面通过灰化进行亲水处理。然后，通过在底部的焊盘电极12上的部分的区域中具有孔的掩模曝光到切割线DL。然后将具有第二抗蚀剂层17的基板10浸渍在显影液20d中以显影第二抗蚀剂层17.当显影液20d到达孔10w的底部和附近时，第二抗蚀剂层17在该区域从焊盘电极12的一部分到切割线DL被可靠地移除，以可靠地暴露第二绝缘膜16的一部分。（C）2006年，JPO和NCIPI

7. 发明专利

JP2006013283A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2006013283A
公开(公告)日：2006-01-12
申请号：JP2004190841
申请日：2004-06-29
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： SEKI YOSHINORI , YAMAGUCHI KEIICHI
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To improve reliability in the patterning process of a negative resist layer and a wiring layer, in the manufacturing method of a semiconductor device.
SOLUTION: After an opening 10w is formed on the rear face of a semiconductor substrate 10, the wiring layer 18 and a third resist layer 19 are formed thereon. A mask 20 is provided above a dicing line DL on the bottom of the opening 10w. The third resist layer 19 is exposed by optic energy such that light reflected from a sidewall to the bottom of the opening 10w does not adhere to the third resist layer 19, corresponding to the mask 20. The third resist layer 19, corresponding to the mask 20, is removed by development. The entire surface of the third resist layer 19 is again exposed. The wiring layer 18 is etched by using the third resist layer 19 as mask. Finally, the semiconductor substrate 10 is diced into a plurality of semiconductor chips along the dicing line DL.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：在半导体器件的制造方法中，为了提高负型抗蚀剂层和布线层的图案化工艺的可靠性。解决方案：在半导体衬底10的背面上形成开口10w之后，在其上形成布线层18和第三抗蚀剂层19。在开口10w的底部的切割线DL的上方设置有掩模20。第三抗蚀剂层19被光能暴露，使得从侧壁反射到开口10w的底部的光不对应于掩模20粘附到第三抗蚀剂层19.第三抗蚀剂层19对应于掩模 20，通过开发删除。第三抗蚀剂层19的整个表面再次暴露。通过使用第三抗蚀剂层19作为掩模来蚀刻布线层18。最后，半导体衬底10沿着切割线DL切割成多个半导体芯片。版权所有（C）2006，JPO＆NCIPI

8. 发明专利

JP2005311117A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005311117A
公开(公告)日：2005-11-04
申请号：JP2004126917
申请日：2004-04-22
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： YAMAGUCHI KEIICHI , TAKAO YUKIHIRO , ISHIBE SHINZO , NOMA TAKASHI , KANAMORI HIROSHI
IPC分类号： H01L23/52 , H01L21/3205
摘要： PROBLEM TO BE SOLVED: To obtain a high reliability high-density mounting semiconductor device exhibiting superior productivity. SOLUTION: A groove 20, having a depth to the middle of thickness of a semiconductor chip 50, is formed in the semiconductor chip 50. The semiconductor chip 50 is divided into a first semiconductor region 50A (semiconductor thickness t1) where the groove 20 is not formed, and a second semiconductor region 50B (semiconductor thickness t2) which has become thinner than the first semiconductor region 50A, because the groove 20 has been formed. Furthermore, a via hole 21 is formed to penetrate the second semiconductor region 50B of the semiconductor chip 50. The rear surface of the semiconductor chip 50 and the sidewall of the via hole 21 are coated with an insulation layer 22. A wiring layer 23 is formed to extend over the rear surface of the semiconductor chip 50, i.e. over the first semiconductor region 50A and the second semiconductor region 50B, while being connected with pad electrodes 11 and 11 through the via hole 21. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：获得具有优异生产率的高可靠性高密度安装半导体器件。解决方案：在半导体芯片50中形成具有半导体芯片50的厚度中间的深度的凹槽20.半导体芯片50被分成第一半导体区域50A（半导体厚度t1）由于槽20已经形成，所以不形成槽20，并且已经变得比第一半导体区域50A薄的第二半导体区域50B（半导体厚度t2）。此外，形成通孔21以穿透半导体芯片50的第二半导体区域50B。半导体芯片50的后表面和通孔21的侧壁涂覆有绝缘层22.布线层23是形成为在半导体芯片50的后表面上延伸，即在第一半导体区域50A和第二半导体区域50B之上，同时通过通孔21与焊盘电极11和11连接。（C） 2006年，JPO＆NCIPI

9. 发明专利

JP2005072554A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005072554A
公开(公告)日：2005-03-17
申请号：JP2004022989
申请日：2004-01-30
申请人： Kanto Sanyo Semiconductors Co Ltd , Sanyo Electric Co Ltd , 三洋電機株式会社 , 関東三洋セミコンダクターズ株式会社
发明人： NOMA TAKASHI , SUZUKI AKIRA , KITAGAWA KATSUHIKO , SEKI YOSHINORI , TAKAO YUKIHIRO , YAMAGUCHI KEIICHI , WAKUI MOTOAKI , OTSUKA HISAO , IIDA MASANORI
IPC分类号： H01L23/12 , H01L21/301 , H01L23/31 , H01L23/485
CPC分类号： H01L24/13 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3114 , H01L24/11 , H01L24/12 , H01L2221/68327 , H01L2221/68372 , H01L2224/02313 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/131 , H01L2224/13144 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/00014 , H01L2224/13099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device formed in a package and its manufacturing method by which a yield and reliability is enhanced. SOLUTION: In a semiconductor substrate 302, a window 303 to expose a first wiring 301 is formed only in a region where the first wiring 301 exists, by which an area where the semiconductor substrate 302 bonds with a glass substrate not illustrated through an insulation film and a resin is increased to prevent cracks and peeling. After the window 303 is formed, a slit is formed along a dicing line, and then the slit is covered with a protection film, after which the semiconductor device is diced into individual semiconductor chips for separation. Thus, the occurrence of peeling at a cross section and an edge of the separated semiconductor chips caused by contact of a blade is suppressed to the utmost. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种形成在封装中的半导体器件及其制造方法，其产率和可靠性得到提高。解决方案：在半导体衬底302中，仅在第一布线301存在的区域中形成露出第一布线301的窗口303，半导体衬底302与未图示的玻璃衬底接合的区域增加绝缘膜和树脂以防止裂纹和剥离。在形成窗口303之后，沿着切割线形成狭缝，然后用保护膜覆盖狭缝，然后将半导体器件切割成单独的半导体芯片以进行分离。因此，最大限度地抑制了由叶片的接触引起的分离的半导体芯片的截面和边缘的剥离现象。版权所有（C）2005，JPO＆NCIPI

10. 发明专利

JP2006173198A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006173198A
公开(公告)日：2006-06-29
申请号：JP2004360298
申请日：2004-12-13
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： YAMAGUCHI KEIICHI
IPC分类号： H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To solve the problem that chemical for processing and impurities in atmosphere invade into a device through a crack as a route when the crack goes into a glass substrate bonded to a device-side during the work processing of a semiconductor wafer and that inconvenience occurs in the semiconductor device. SOLUTION: The semiconductor device is provided with a support body 4 bonded to a semiconductor substrate where first wiring 3 is formed through adhesive, second wiring 8 which is connected to first wiring 3 and is extended to the rear face of the semiconductor substrate through an insulating film 6, and a protection film 10 formed on second wiring 8. In the support body 4, a substrate 4a formed of resin and the glass substrate 4b are laminated. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：为了解决在加工工序中，当裂纹进入与装置侧接合的玻璃基板时，通过裂纹作为路径，解决了加工用化学品和大气中杂质侵入装置的问题半导体晶片，并且在半导体器件中发生不便。解决方案：半导体器件设置有接合到半导体衬底的支撑体4，第一布线3通过粘合剂形成，第二布线8连接到第一布线3并延伸到半导体衬底的背面通过绝缘膜6和形成在第二布线8上的保护膜10.在支撑体4中，层叠由树脂形成的基板4a和玻璃基板4b。版权所有（C）2006，JPO＆NCIPI

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