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1. 发明专利

JPH03259537A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03259537A
公开(公告)日：1991-11-19
申请号：JP5639890
申请日：1990-03-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TSUNODA HIDEKI , YOSHIDA ISAO , GOSHIMA HIDEKAZU , OTAKA SHIGEO , ISHIZAKA KATSUO , KASHU NOBUYOSHI
IPC分类号： H01L21/322 , H01L21/336 , H01L29/32 , H01L29/78
摘要： PURPOSE:To suppress other characteristic deterioration to a minimum limit, to improve switching speed and to increase breakdown strength by forming a crystal defect layer due to an ion implantation near a base region, and introducing a life time killer to a power MOSFET. CONSTITUTION:A p-type diffused region 103 is formed on an n-type high concentration substrate 101 having a drain electrode 109 and a base region 102 of an n-type low concentration region, and an n-type high concentration diffused region 104, etc., to become a source region is formed by high concentration ion implantation with dopant as carbon, thereby forming a power MOSFET. A crystal defect layer 110 is formed near the region 102 by the predetermined ion implantation, a life time killer is introduced to the MOSFET by the layer 110 to suppress the deterioration of other characteristic to a minimum limit, the reverse recovery time of a flywheel diode is shortened, and switching speed, breakdown strength are enhanced.

2. 发明专利

JP2004247559A Semiconductor device and method for manufacturing the same 审中-公开
公开(公告)号：JP2004247559A
公开(公告)日：2004-09-02
申请号：JP2003036459
申请日：2003-02-14
申请人： Elpida Memory Inc , Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , エルピーダメモリ株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： NAKAMURA YOSHITAKA , GOSHIMA HIDEKAZU , ASANO ISAMU , HORIKAWA TSUGUHIRO , KUROKI KEIJI , SAKUMA HIROSHI , KOYANAGI KENICHI , KAWAGOE TAKESHI
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/768 , H01L27/108 , H01L29/76
CPC分类号： H01L28/65 , H01L21/7687 , H01L27/10814 , H01L27/10852
摘要： PROBLEM TO BE SOLVED: To provide an MIM type capacitor where only the bottom of a lower electrode is thick, and to provide a method for manufacturing the capacitor while reducing the number of processes and securing a margin at a joint. SOLUTION: This semiconductor device is composed of an MISFET for memory cell selection formed on one main surface of a semiconductor substrate, and a memory cell having a capacitor element composed of the lower electrode 41 electrically connected with the source or drain of the MISFET for memory selection at the bottom via a first metal layer and an upper electrode 61 formed at the top of the lower electrode 41 via a capacitor insulation film 51. The film thickness at the bottom of the lower electrode 41 is made to be ≥30 nm. Only the bottom of the capacitor is made to be thick by applying the sputtering of a high ionization rate and high directivity such as a PCM method to the forming of the lower electrode 41. COPYRIGHT: (C)2004,JPO&NCIPI

3. 发明专利

JP2001177072A METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001177072A
公开(公告)日：2001-06-29
申请号：JP36350299
申请日：1999-12-21
申请人： HITACHI LTD
发明人： KUWANO SATOSHI , NISHIHARA SHINJI , SAWARA MASASHI , YAMADA KENTARO , TANAKA KATSUHIKO , TAMARU TAKESHI , GOSHIMA HIDEKAZU , YONETANI TOUTA
IPC分类号： H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of contamination caused by the abnormal growth of a titanium nitride film constituting the electrode of a capacitive element. SOLUTION: A sputtered titanium nitride film 27 is interposed between a tantalum nitride film 26 constituting the capacitive insulating film of a capacitive element and a CVD-titanium nitride film constituting a part of an upper electrode, so that it may avoid the influence that the crystal condition of the tantalum oxide film 26 has on the CVD-titanium nitride film 28.

4. 发明专利

JPH02119173A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02119173A
公开(公告)日：1990-05-07
申请号：JP27065288
申请日：1988-10-28
申请人： HITACHI LTD
发明人： GOSHIMA HIDEKAZU , KASHU NOBUYOSHI , OYU SHIZUNORI , SUZUKI TADASHI
IPC分类号： H01L21/761 , H01L21/74 , H01L21/76 , H01L21/8242 , H01L27/08 , H01L27/10 , H01L27/108 , H01L29/47 , H01L29/78 , H01L29/861 , H01L29/872
摘要： PURPOSE:To suppress the leakage current of a p-n junction and save the power consumption and realize high speed operation by a method wherein a first buried impurity layer of p-type which is the conductivity type of a substrate and an n-type second buried impurity layer are formed and the higher maximum impurity concentration is given to the second impurity layer. CONSTITUTION:After an element isolation oxide film 5 is formed on a substrate 4, boron B ions are implanted to form a B-implanted layer 6. Then a first buried impurity layer 7 of p-type which is the conductivity type of the substrate 4 is formed and, in a region deeper than the layer 7, a second buried layer 8 having the higher maximum impurity concentration is formed. If the impurity is activated by annealing in a nitrogen atmosphere, the layer 6, layer 7 and layer 8 are turned into a p-type layer, a p-type buried layer and an n-type buried layer respectively. Then As ions are implanted and a high impurity concentration n-type region 9 is formed in the surface of the substrate 4 by annealing to form a p-n junction. With this constitution, the surface integral of the leakage current of the p-n junction can be suppressed and the power consumption of an LSI can be saved and the high speed operation of the LSI can be realized.

5. 发明专利

JPS6444078A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6444078A
公开(公告)日：1989-02-16
申请号：JP19969787
申请日：1987-08-12
申请人： HITACHI LTD
发明人： SUZUKI TADASHI , KASHU NOBUYOSHI , OYU SHIZUNORI , GOSHIMA HIDEKAZU
IPC分类号： H01L39/22 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To eliminate a stress at least to a semiconductor substrate even if a composite structure of a superconductor and a semiconductor is cooled to a super-low temperature by providing a stress buffer layer between a superconducting material section and a semiconductor section. CONSTITUTION:A layer 2 for buffering a distortion or a stress is provided between a superconductor 3 and a semiconductor 1. That is, the stress due to the difference of the thermal expansion coefficients of both the materials is absorbed by the buffer layer provided between both the materials to eliminate the distortion, stress in both the materials. Thus, even if a composite structure of the superconductor and the semiconductor is cooled to a super-low temperature, no stress is applied to the superconductor and the semiconductor. Accordingly, a high speed semiconductor device having high reliability can be performed.

6. 发明专利

JPH11214644A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH11214644A
公开(公告)日：1999-08-06
申请号：JP1261498
申请日：1998-01-26
申请人： HITACHI LTD
发明人： SAITO MASAYOSHI , NAKAMURA YOSHITAKA , GOSHIMA HIDEKAZU , KAWAKITA KEIZO , YAMADA SATORU , SEKIGUCHI TOSHIHIRO , ASANO ISAMU , TADAKI YOSHITAKA , FUKUDA TAKUYA , SUZUKI MASAYASU , TAMARU TAKESHI , FUKUDA NAOKI , AOKI HIDEO , HIRASAWA MASANARI
IPC分类号： H01L27/108 , H01L21/02 , H01L21/316 , H01L21/768 , H01L21/8242
摘要： PROBLEM TO BE SOLVED: To avoid the failure that lower layer wirings being striped off from the surface of an insulating film due to a high temp. heat treatment, for forming a capacitance insulation film in a DRAM having information storing capacitance elements having capacitance insulation film which is made of a high-dielectric const. material. SOLUTION: In a DRAM having a capacitor-over-bit line structure with a capacitor insulation film of information storing capacitance elements C made of a high-dielectric const. material such as Ta2 O5 film 46, at least a part contacting a base Si oxide film 28 of bit lines BL, laid on a lower layer than information storing capacitance elements C and a part of first layer wirings 23-26 of a peripheral circuit are made from a W film, thereby improving the adhesion of the interface of the bit lines BL and wirings 23-26 to the Si oxide film 28, due to high temp. heat treatment conducted in forming the capacitance insulation film.

7. 发明专利

JPH0971866A REDUCED PRESSURE CVD APPARATUS 失效
公开(公告)号：JPH0971866A
公开(公告)日：1997-03-18
申请号：JP22498695
申请日：1995-09-01
申请人： HITACHI LTD
发明人： MURAOKA KOJI , MIYATA TOSHIMITSU , GOSHIMA HIDEKAZU
IPC分类号： C23C16/44 , C23C16/455 , H01L21/205 , H01L21/285 , H01L21/31
摘要： PROBLEM TO BE SOLVED: To decrease the particles sticking to section exclusive of film forming sections and to decrease the amt. of the dust adhered on wirings by providing a reduced pressure CVD apparatus with gas diffusion chambers for every kind of gases. SOLUTION: The gas, such as WF6 , enters the diffusion chamber 6 via an introducing port 102 and falls against a diffusion plate 4, thereby spreading in the diffusion chamber 103. The gas is passed through a connecting hole 101 and is introduced via a blow-off plate 8 into a film forming chamber 105. The gas, such as SiN4 , is passed through a diffusion chamber 6 and arrives at the diffusion chamber 7 from an introducing port 106 and falls against a diffusion plate 10 and diffuses in a diffusion chamber 104 through connecting holes 101. The gaseous WF6 passed the connecting holes 101 passes the holes 108 bored at the blow-off plate 8. The gaseous SiH4 passes the holes 109 of the blow-off plate 8 and blows out into a film forming chamber 105. The holes 108, 109 are concentrically and alternatively arranged and both gases are uniformly mixed within the film forming chamber 105. The metallic film of tungsten W is formed on a wafer 12 heated by a heater 11.

8. 发明专利

JPH0817762A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0817762A
公开(公告)日：1996-01-19
申请号：JP15090894
申请日：1994-07-01
申请人： HITACHI LTD
发明人： GOSHIMA HIDEKAZU , KOBAYASHI NOBUYOSHI , NAKAMURA YOSHITAKA
IPC分类号： C23C16/08 , C23C16/56 , H01L21/285 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To provide a method for manufacturing a semiconductor where the stress of a high melting-point metal which is formed by the CVD method is reduced and the peeling of the film is prevented. CONSTITUTION:When forming a high melting-point metal film such as W films 16 and 17 by the chemical vapor growth method, the forming of the high melting-point metal film is divided into a plurality of film-formation steps and the film-formation pause period between the film-formation steps, the thickness of the high melting-point film formed at each film-formation step is set to a film thickness which is virtually equal to the film thickness when the average stress of the film is equal to 0, and oxidizing gas such as O2 and nitriding gas such as NH3 are introduced into a film-formation chamber during each film-formation suspension period, thus oxidizing, nitriding, or oxidizing/nitriding the surface of the high melting-point metal film.

9. 发明专利

JPH04211123A FORMATION OF METAL OR METAL SILICIDE FILM 失效
公开(公告)号：JPH04211123A
公开(公告)日：1992-08-03
申请号：JP754891
申请日：1991-01-25
申请人： HITACHI LTD
发明人： KOBAYASHI NOBUYOSHI , GOSHIMA HIDEKAZU , SUZUKI MASAYASU , HONMA YOSHIO , YOKOYAMA NATSUKI
IPC分类号： C23C16/04 , C23C16/08 , C23C16/42 , H01L21/28 , H01L21/285
摘要： PURPOSE:To realize security of high selectivity in selective growth and high step coverage of a metal film and an interfacial state with a substrate in overall growth by controlling surface reaction in a metal CVD. CONSTITUTION:A W wiring 7 of excellent step coverage can be formed with a connection hole filled with a W film 9 in high selectivity by CVD wiring fluoro silane (SiH2F2, SiHF3, etc.) for a metal halide (WF6, etc.)

10. 发明专利

JPH02130832A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH02130832A
公开(公告)日：1990-05-18
申请号：JP28359288
申请日：1988-11-11
申请人： HITACHI LTD
发明人： SUZUKI TADASHI , GOSHIMA HIDEKAZU , KASHU NOBUYOSHI , OYU SHIZUNORI
IPC分类号： H01L29/73 , H01L21/331 , H01L21/74 , H01L21/76 , H01L21/761 , H01L21/8238 , H01L27/092 , H01L29/732
摘要： PURPOSE:To obtain a structure being able to avoid a bad influence on the device by the arising of driven impurities at a mask edge, when an embedded layer is formed only at a limited region, by driving high-energy ions into a substrate patterned with a mask. CONSTITUTION:A groove filled with an insulator 4 is formed, at a mask edge section, when an embedded layer 3 is formed by driving ions through the mask 2 formed on a semiconductor substrate 1. Incidentally, it does not matter whether the process of forming this insulator 4 is before the process of driving ions or after it. This vanishes impurity doping of inconvenient regions, being cause of a short circuit with the substrate surface region, etc., when the embedded layer 3 is formed at a specified region restricted in the transverse direction by the use of drive-in of high-energy ions. Accordingly, the embedded layer 3 suitable for device application can be formed.

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