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1. 发明专利

JPH07147569A INSERTION CIRCUIT FOR MONITOR DATA 失效
公开(公告)号：JPH07147569A
公开(公告)日：1995-06-06
申请号：JP29229893
申请日：1993-11-24
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： HASEGAWA HITOSHI , TANIGUCHI IKUO , OTA HIROSHI , UEDA HIROMI
IPC分类号： H04J3/12 , H04J3/14
摘要： PURPOSE:To maximize number of data insertion circuits within a predetermined time by inserting monitor data within a predetermined period and keeping an entire average monitoring data insertion period to be a predetermined period of a valid frame. CONSTITUTION:The circuit has a count section 10, a data insertion section 30, and an alarm detection section 20, the count section 10 receives an enable signal and a data insertion end flag and outputs carry-out for each N-th valid frame and sends a data insertion enable flag set for each N valid frame or cleared in a data insertion end flag. The data insertion section 30 receives the data insertion enable flag and inserts monitor data to a first idle frame while the data insertion enable flag continues the set state and sends the data insertion end flag. The alarm detection section 20 outputs an alarm set when carry-out is received when the data insertion enable flag is set and cleared when the data insertion end flag is received.

2. 发明专利

JPH03252143A SEMICONDUCTOR PROCESSING EQUIPMENT 失效
公开(公告)号：JPH03252143A
公开(公告)日：1991-11-11
申请号：JP4983590
申请日：1990-03-01
申请人： FUJITSU LTD
发明人： KOBAYASHI MASANORI , HASEGAWA HITOSHI , SHIRAKAWA YOSHIMI
IPC分类号： H01L21/60 , H01L21/321
摘要： PURPOSE:To enable uniform formation of bumps on a semiconductor substrate by providing a drip pan in the upper outer peripheral edge of an electrolyte bath used in forming metal bumps. CONSTITUTION:This equipment comprises a substrate holder 1 and an electrolyte bath: the former functions as the cathode with a semiconductor substrate 4 to form bumps 3 by electroplating; and the latter is supplied with electrolyte 6 from below to fill it by overflow of the upper peripheral edge, gets the substrate holder 1 with the semiconductor substrate below contact the liquid surface, and is furnished with an anode plate 7 in the bottom, and with a drip pan 8 in the upper outer peripheral edge. This structure allows flattening of the liquid surface of electrolyte which contacts the substrate and uniform contact of the substrate periphery with electrolyte as well as its center. It follows that bumps of uniform configuration are formed in the substrate periphery.

3. 发明专利

JPH03240992A ELECTROPLATING DEVICE 失效
公开(公告)号：JPH03240992A
公开(公告)日：1991-10-28
申请号：JP3547790
申请日：1990-02-15
申请人： FUJITSU LTD
发明人： SHIRAKAWA YOSHIMI , OGAWA TSUTOMU , HASEGAWA HITOSHI
IPC分类号： C25D5/08 , C25D7/12 , H01L21/321 , H01L21/60
摘要： PURPOSE:To form a plated film having uniform film thickness on the material to be plated by placing a granular plating member on a lamellate electrode having network holes in the midway part wherein plating liquid reaches the material to be plated. CONSTITUTION:An electroplating device is constituted of a first lamellate electrode 8 having network holes, a plurality of granular plating members 9 placed on the single face thereof, a second electrode 10 connected to the material 11 to be plated and a plating tank. The plating members 9 allowed to flow out into plating liquid uniformly reach the material 11 to be plated. A plated film having uniform film thickness is formed. Since the first electrode 8 is formed of material insoluble into plating liquid and the plating members 9 are made granular, the plane shape of the electrode constituted of the first electrode 8 and the plating members 9 is not changed even when plating is repeated. The electric field distribution between the material 11 to be plated and the first electrode 8 is held constant. The velocity wherein the plating members 9 are eluted is held constant.

4. 发明专利

JPH02237032A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH02237032A
公开(公告)日：1990-09-19
申请号：JP5605089
申请日：1989-03-10
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI , NAWATA TAKAHARU , KANEDA HIROSHI , SUZUKI UDE , SHIRAKAWA YOSHIMI
IPC分类号： H01L21/322
摘要： PURPOSE:To form a device region developing the least crystalline defect for bearing the excellent characteristics by a method wherein one conductivity type impurity diffused layer is formed on the surface of the first semiconductor substrate; gettering windows are selectively made in the part of the insulating film (impurity diffused layer); and then the device is formed in the second semiconductor layer in the same conductivity as that of the impurity diffused layer. CONSTITUTION:A polysilicon layer 12 is formed e.g. on the first p type silicon wafer 11 and then p type layer 13 is formed by ion-implanting boron. The polysilicon layer 12 is selectively etched away to leave the polysilicon making gettering windows 14 but at this time, a p type impurity diffused layer 13a is left without being etched away on the surface of the silicon wafer 11. Next, the whole surface is coated with a spin on glass(SOG) 15 by flattening process and then the SOG 15 on the silicon wafer 11 is heat-treated for flattering and thinning processes to form the second silicon layer 16 for device formation. Finally, a specified device 18 is formed in the region encircled by SiO2 layers 17 and connecting to the gettering windows 14. Through these procedures, any crystalline defect can be obviated to enhance the device characteristics.

5. 发明专利

JPH01138718A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01138718A
公开(公告)日：1989-05-31
申请号：JP29726287
申请日：1987-11-25
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI
IPC分类号： H01L21/768 , H01L21/288
摘要： PURPOSE:To contrive improvement both in tight adhesion and barrier property between a buried metal and a semiconductor substrate by a method wherein a barrier metal, having affinity to both of semiconductor and a plating metal, which prevents the diffusion of plated metal to a semiconductor substrate, is adhered in advance. CONSTITUTION:The surface of a P-type Si substrate 21 is covered by a PSG film having an aperture part 5 to be used to lead out an electrode, and an N region is provided. TiW 25, which has affinity to both of semiconductor Si and plating metal and prevents the diffusion of Au to Si, is deposited on the whole surface of the substrate 21. Then, using a resist 26 which will be peeled off as a mask, the TiW 25 is removed excluding the electrode lead-out part 5 and its circumference. The substrate 21 is dipped into an Au electrolyte with substrate side in negative potential. At this time, a light is projected from the rear side of the substrate 21, the backward current of the P-N junction is increased, and Au plating is grown. Then, after TiW 28, which has affinity with both of Au and the wiring metal of Al has been deposited on the whole surface, Al is deposited, patterning is conducted, and an Al wiring is formed.

6. 发明专利

JPS6474744A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6474744A
公开(公告)日：1989-03-20
申请号：JP23300387
申请日：1987-09-17
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI , KOBAYASHI MASANORI , KASE MASATAKA
IPC分类号： H01L21/60
摘要： PURPOSE:To equalize the growth rate of a plating and to form a bump of an even film thickness by a method wherein a plating object region is divided into at least two regions of the central part of a semiconductor wafer and the outer peripheral part of the wafer through a scribing line and the plating is controlled on every region. CONSTITUTION:A barrier metallic film 22 on a semiconductor wafer 2 is removed along a scribing line 22c to pass on the peripheral edge end of a range reduced 1/2r from its radius (r) and plating object regions A and B, each consisting of each of barrier metallic films 22a and 22b, are formed. Then, the wafer 21 is set on a jet system plating device, a gold plating solution is blown up through a solution jet part 26 while a prescribed temperature is maintained and a plating is grown on a bump contact window part. Moreover, a plating current is controlled through plating control circuits 23 and 24 for the regions A and B. Thereby, even though a difference is generated between the amount of the plating solution to reach the central part of the plating object region of the wafer 2 and the amount of the plating solution, which is diffused on the outer peripheral part of the wafer and reaches the central part, the growth rate of the plating can be equalized.

7. 发明专利

JPS6465858A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6465858A
公开(公告)日：1989-03-13
申请号：JP22123287
申请日：1987-09-05
申请人： FUJITSU LTD
发明人： KASE MASATAKA , HASEGAWA HITOSHI , OGAWA TSUTOMU , UNO MASAAKI
IPC分类号： H01L21/60 , H01L21/027 , H01L21/30
摘要： PURPOSE:To improve a material in a utilization factor by a method wherein a bump is formed in such a manner that an electroplating is performed using a bump forming mask and a metallic layer is formed only on a bump forming region of a non-defective semiconductor device. CONSTITUTION:Semiconductor device elements formed on a semiconductor wafer 1 are made to be individually tested so as to find each of the semiconductor device elements defective or non-defective. Next, a positive-type resist film 5 is formed on the wafer 1. Then, a first mask 7 provided with transparent regions corresponding to the bump forming regions of the whole semiconductor device elements formed on the wafer 1 and a second mask 8, which is provided with transparent regions that correspond to the whole face of the non-defective semiconductor device elements, consisting of a liquid crystal shutter or the like are provided. The exposure and the development are performed using these masks 7 and 8 overlapped with each other so as to form a bump forming resist mask 9 provided with opening corresponding to the bump forming regions of the nob-detective semiconductor device elements. By the use of the mask 9, only the above openings are plated through an electroplating method so as to form a bump 6 and the mask 9 and a metal 4 are removed.

8. 发明专利

JPS6373644A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6373644A
公开(公告)日：1988-04-04
申请号：JP21732686
申请日：1986-09-17
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI
IPC分类号： H01L21/3205
摘要： PURPOSE:To prevent wirings from disconnection that takes place as they become minute while flattening the upper part of a throughhole by a method wherein a measure is taken to make a low melting point metal flow from a barrier metal buried in the throughhole made in an insulating film to the insulating film to bury the upper side of throughhole. CONSTITUTION:A barrier metal 13 is buried in a throughhole 11a leaving the upper part side thereof 11a. A three layer structure of Al (primary layer)/Ti/Ni(surface) is recommended for the barrier metal 13 to prevent it from being penetrated. The barrier metal 13 leaving the upper part thereof is buried in the throughhole 11a by lift off process. Next, a low melting point metal 14 evaporated on overall surface is patterned (as shown by a dotted line) leaving itself in volume almost equivalent to that of upper space in the throughhole 11a. When the low melting point metal 14 is heated up to the temperature near the melting point, the contact angle with an insulating film 11 is gradually made larger taking a bump sampe so that the metal 14 may flow in the arrow direction down into the throughhole 11a. Finally, an Al interconnection 16 is formed on the low melting point metal 14 with another barrier metal 15 laid between them.

9. 发明专利

JPS6358858A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6358858A
公开(公告)日：1988-03-14
申请号：JP20303586
申请日：1986-08-28
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To strengthen a metal bump in adhesiveness by a method wherein a barrier metal film surrounding an electrode region is subjected to etching for the formation of a groove, a bump material film is attached to the electrode upper portion, and then etching is accomplished, after plating the electrode upper portion with metal, of the surrounding barrier metal film. CONSTITUTION:An aluminum electrode 12 is built on a semiconductor substrate 11, a phosphosilicate glass film 13 is formed, a resist film patter 14 is proved, and then an opening 15 is provided. Next, a barrier metal film 16 is attached A process follows wherein a resist film pattern 17 is formed, and a groove 18 is formed. A solder film 19 is attached, a resist film pattern 20 is provided, and etching is performed for the removal of the solder film 19 except from the electrode 12. A resist film pattern 21 is provided and a thick solder bump 22 is attached by plating. Finally, etching is accomplished for the removal of the exposed barrier metal 16, for the completion of a hemisphere-geometry solder bump 22.

10. 发明专利

JPS6356941A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6356941A
公开(公告)日：1988-03-11
申请号：JP20010186
申请日：1986-08-28
申请人： FUJITSU LTD
发明人： HASEGAWA HITOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To prevent the side etching of a barrier metal on the lower side of a bump, and to improve electrical connection with a wiring by depositing a substance as a stopper for etching to the predetermined section of the barrier metal before or at the same time as the bump is formed. CONSTITUTION:A barrier metal 4 is removed, electroplating using a barrier metal 4a as a cathode is conducted, and gold 10 is deposited to barrier-metal removing sections (a) as a substance as a stopper. The deposition of gold 10 is started from the barrier metal 4a at the initial stage of the electroplating, and gold 10 grows in the upward direction and the cross direction, and reaches a barrier metal 4b. When sections except a bump forming region are masked with a resist 11 and a bump 6 is shaped through plating, the bump 6 grows from the upper sections of gold 10 and the barrier metal 4b, and takes a mushroom shape. Lastly, the resist 11 is removed, and the barrier metal 4a is gotten rid of through etching. Even when the bump 6 is to some extent side-etched during the etching, gold 10 functions as a stopper for etching after gold 10 is exposed.

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