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1. 发明专利

JP2006066767A Electronic component mounting device 有权
标题翻译：电子元件安装设备
公开(公告)号：JP2006066767A
公开(公告)日：2006-03-09
申请号：JP2004249675
申请日：2004-08-30
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NISHIMURA TAKAO , NAKAMURA KOICHI , TAKASHIMA AKIRA , KIRA HIDEHIKO
IPC分类号： H05K13/04
摘要： PROBLEM TO BE SOLVED: To mount an electronic component at a suitable position by preventing dirt on an anti-adhesion tape or a shift therein. SOLUTION: An anti-adhesion tape 30 has openings 31 spaced at predetermined intervals. A bonding tool 10 has suction holes 11b, 11c for sucking the anti-adhesion tape 30, and a suction hole 11a for sucking an electronic component 40 from an opening 31. A bonding head 20 moves the bonding tool 10 having the electronic component 40 sucked thereto upwards or downwards to mount the electronic component 40 onto a board 80 having an adhesive 70 applied thereonto. After the electronic component 40 is mounted, a feeder supplies the anti-adhesion tape 30 in such a manner that the electronic component 40 is sucked from an opening 31 not used yet. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过防止防粘附带上的污垢或其中的位移来将电子部件安装在合适的位置。防粘带30具有以预定间隔隔开的开口31。接合工具10具有用于吸附防粘带30的吸孔11b，11c和用于从开口31吸取电子部件40的吸孔11a。接合头20使具有吸附的电子部件40的接合工具10移动向上或向下以将电子部件40安装到其上施加有粘合剂70的板80上。在安装电子部件40之后，馈电器以这样的方式供应防粘带30，使得电子部件40从尚未使用的开口31被吸入。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2006013544A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006013544A
公开(公告)日：2006-01-12
申请号：JP2005240362
申请日：2005-08-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ANDO FUMIHIKO , TAKASHIMA AKIRA , NISHIMURA TAKAO , NOMOTO TAKASHI , KASHU MASANORI
IPC分类号： H01L21/60 , H01L21/607
CPC分类号： H01L24/81 , H01L2224/14 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent short circuiting from occurring between bumps, even if a pitch between bumps becomes narrow, in a method of manufacturing a semiconductor device, in which a projecting electrode provided in a semiconductor chip is bonded to a pad provided in a mounted component.
SOLUTION: In the method of manufacturing the semiconductor device which has a step of ultrasonic bonding the projecting electrode, provided in the semiconductor chip to pads 15A and 15B provided in a mother chip 3B in which the semiconductor chip is mounted; a disposed pitch (Py) between the pads 15B which extend in the direction (Y direction) perpendicular to the amplitude direction (X direction) of ultrasonic waves is set longer than the disposed pitch (Px) between the pads 15A, which extends in the same direction as the amplitude direction (X direction) of the ultrasonic waves.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题为了防止在凸块之间发生短路，即使在凸起之间的间距变窄的情况下，在制造半导体器件的方法中，其中设置在半导体芯片中的突出电极接合到衬垫提供在安装的组件中。解决方案：在制造半导体器件的方法中，该半导体器件具有将设置在半导体芯片中的突起电极与设置在其中安装有半导体芯片的母芯片3B中的焊盘15A和15B超声波接合的步骤; 在与超声波的振幅方向（X方向）垂直的方向（Y方向）上延伸的焊盘15B之间的配置间距（Py）被设定为长于在该延伸的焊盘15A之间的设置间距（Px）与超声波的振幅方向（X方向）相同的方向。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005333167A Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：JP2005333167A
公开(公告)日：2005-12-02
申请号：JP2005240363
申请日：2005-08-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： ANDO FUMIHIKO , TAKASHIMA AKIRA , NISHIMURA TAKAO , NOMOTO TAKASHI , KASHU MASANORI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16145 , H01L2224/32145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent occurrence of a short-circuit between bumps even if pitches between the bumps are made narrow in the manufacturing method of a semiconductor device where a projection electrode installed in the semiconductor chip is bonded to a pad arranged in a member to be mounted. SOLUTION: The manufacturing method of the semiconductor device has a process for bonding stud bumps 8B disposed in a daughter chip 2B to the pads 15 arranged in a mother chip 3B, and a process for electrically connecting a probe 25 to the pads 15 by stabbing the probe to the pad and conducting a test of the mother chip 3B is formed. When the stud bumps 8B are bonded to the pads 15, recesses 26 whose shapes are sequentially extended toward opening ends formed in the pads 15 and tapered small projections 27 formed at tip parts of the stud bumps 8B are engaged and are bonded by the probe 25. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止在半导体器件的制造方法中使凸起之间的间距窄的情况下发生凸点之间的短路，其中安装在半导体芯片中的投影电极被接合到布置的焊盘在一个会员被安装。解决方案：半导体器件的制造方法具有将布置在母芯片3B中的焊盘15配置在子芯片2B中的突起凸块8B接合到将芯片25与焊盘15电连接的工序通过将探针刺入垫并形成母芯片3B的测试。当凸块8B接合到焊盘15上时，形成为形成在焊盘15中的开口端的形状的凹部26和形成在凸块凸块8B的尖端部分的锥形小突起27接合并通过探针25 （C）2006年，JPO＆NCIPI

4. 发明专利

JP2003347390A Mark recognizing method, method of manufacturing semiconductor device and packaging method 有权
标题翻译：标记识别方法，制造半导体器件的方法和包装方法
公开(公告)号：JP2003347390A
公开(公告)日：2003-12-05
申请号：JP2002153519
申请日：2002-05-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： WATABE MITSUHISA , KUMAGAI KINICHI , TAKASHIMA AKIRA
IPC分类号： H01L21/68 , G01B11/00 , G01R31/26 , G03F9/00 , G06K9/00 , H01L21/00 , H01L21/50 , H01L21/66 , H01L21/683 , H01L21/78 , H01L21/784 , H01L23/44 , H01L23/544
CPC分类号： H01L21/78 , H01L21/67092 , H01L21/681 , H01L23/44 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To recognize an image of a recognition mark which is formed on the circuit pattern formation side of a silicon wafer from the back thereof. SOLUTION: Back grinding is performed until the thickness of a silicon wafer 1 becomes 5-50 μm. The side of the silicon wafer 1 formed with a circuit pattern 2 is irradiated with white light or visible light of a wavelength of ≤800 nm, the visible light transmitted through the silicon wafer 1 is received by a visible light camera 3 from the back side of the silicon wafer 1, and the image of the recognition mark formed on the circuit pattern formation side of the silicon wafer 1 is recognized. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：从其背面识别形成在硅晶片的电路图案形成侧上的识别标记的图像。
解决方案：进行背面磨削直到硅晶片1的厚度变为5-50μm。用形成有电路图案2的硅晶片1的一侧用白光或波长≤800nm的可见光照射，透过硅晶片1的可见光被可见光照相机3从背面接收并且识别形成在硅晶片1的电路图案形成侧的识别标记的图像。版权所有（C）2004，JPO

5. 发明专利

JP2003068974A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2003068974A
公开(公告)日：2003-03-07
申请号：JP2001258712
申请日：2001-08-28
申请人： Fujitsu Ltd , 富士通株式会社
发明人： OZAWA KANAME , HIRAOKA TETSUYA , TAKASHIMA AKIRA
IPC分类号： H01L23/12 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16145
摘要： PROBLEM TO BE SOLVED: To enable a semiconductor device capable of coping with a high speed operation and high-level functions to be reduced in size and weight and improved in electrical properties.
SOLUTION: A semiconductor device is equipped with a first semiconductor device 22 and a second semiconductor device 23, solder balls 26, and a board 24 connecting the semiconductor elements 22 and 23 and the solder balls 26. Metal layers 37 and 38 are formed on the surfaces of the semiconductor devices 22 and 23, and power supply pads 33 inside the electrode pads of the semiconductor devices 22 and 23 are electrically connected to the metal layers 37 and 38 respectively.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了能够实现能够应对高速运转的半导体器件，并且能够降低尺寸和重量以及改善电性能的高级功能。解决方案：半导体器件配备有第一半导体器件22和第二半导体器件23，焊球26和连接半导体元件22和23与焊球26的板24.金属层37和38形成在半导体器件22和23的表面以及半导体器件22和23的电极焊盘内部的电源焊盘33分别电连接到金属层37和38。

6. 发明专利

JP2002299513A SURFACE MOUNT PART AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002299513A
公开(公告)日：2002-10-11
申请号：JP2001102040
申请日：2001-03-30
申请人： FUJITSU LTD
发明人： SUGATA TAKASHI , TAKASHIMA AKIRA , TANIGUCHI FUMIHIKO
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To stabilize electrical connection of a surface mount part having a terminal structure such as land/grid/array to an electrode on a mounting substrate on which the surface mounting part is mounted while a mounting height is suppressed. SOLUTION: A surface mount part comprising an external connection terminal such as land/grid/array is provided, where a pre-coat solder layer is provided on the surface of the external connection terminal.

7. 发明专利

JP2002050737A SEMICONDUCTOR ELEMENT LAMINATE AND METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002050737A
公开(公告)日：2002-02-15
申请号：JP2000234863
申请日：2000-08-02
申请人： FUJITSU LTD
发明人： TANIGUCHI FUMIHIKO , TAKASHIMA AKIRA
IPC分类号： H01L23/12 , H01L23/485 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor element laminate and semiconductor device, where an electrode of each laminated semiconductor element can be drawn out using a simple structure. SOLUTION: In a plurality of wafers 2, each formed with a plurality of semiconductor elements, corresponding electrodes of adjacent semiconductor elements 4 are bonded by bonding wires 6 across a boundary line between these semiconductor elements. A resin layer 8 is formed on a circuit-forming face of each wafer 2, and the bonding wires 6 are embedded in the resin layer 8. A plurality of wafers 2 are laminated to form a single body. The integrated wafers 2 and resin layers 8 are cut along the boundaries between the semiconductor elements 4. Cut end faces 6a of the bonding wires 6 are exposed on the side faces of the resin layers 8.

8. 发明专利

JP2001319988A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001319988A
公开(公告)日：2001-11-16
申请号：JP2000133763
申请日：2000-05-02
申请人： FUJITSU LTD
发明人： UNO TADASHI , TAKASHIMA AKIRA
IPC分类号： H01L23/28 , H01L23/12 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that has a simple configuration applying the structure of a package with a conventional chip size and a small packaging area, and can be vertically packaged for the semiconductor device where a package is vertically arranged to a packaging substrate for reducing the packaging area. SOLUTION: A semiconductor chip 6 is mounted onto a first surface 4a where the wiring pattern of a flexible circuit substrate 4 is formed. A solder ball 8 is formed on a second surface 4b at a side opposite to the first surface. The semiconductor chip 6 is resin-sealed to form a sealing part 10. The side of the surface 4a where the soldering ball 8 is formed is resin-sealed to form a sealing part 12. The circuit substrate 4 is bent for bonding the sealing part 12 to the sealing part 10.

9. 发明专利

JP2001274187A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2001274187A
公开(公告)日：2001-10-05
申请号：JP2000082734
申请日：2000-03-23
申请人： FUJITSU LTD
发明人： TANIGUCHI FUMIHIKO , TAKASHIMA AKIRA , UNO TADASHI
IPC分类号： H01L23/12 , H01L21/60
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can be enhanced in electrical characteristics and assembled at a low cost. SOLUTION: A semiconductor device is equipped with an interposer 14, which is mounted with a semiconductor chip 12 and equipped with bonding pads and ball lands, wires 16 which connect the electrode pads of the semiconductor chip 12 to the bonding pads of the interposer 14, and conductive balls connected to the ball lands of the interposer 14, where the bonding pads and ball lands are formed as conductive pieces 24 and 26 in common. One conductive piece comprising the bonding pad and ball land and the other conductive piece comprising the bonding pad and ball land are arranged to confront each other, so that a semiconductor device of this constitution is capable of coping with signals which need high-speed transmission.

10. 发明专利

JP2000068409A MANUFACTURE OF SEMICONDUCTOR DEVICE, CIRCUIT BOARD AND THE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000068409A
公开(公告)日：2000-03-03
申请号：JP24065098
申请日：1998-08-26
申请人： FUJITSU LTD
发明人： TAKASHIMA AKIRA , KAMIMURA KAZUYA , KUMAGAI KINICHI
IPC分类号： H01L23/12 , H01L21/48 , H01L21/60 , H05K3/34 , H05K3/40
摘要： PROBLEM TO BE SOLVED: To enable solder balls to be mounted reliably on a substrate, even if the diameter dimension of apertures formed in the substrate becomes smaller in a semiconductor device, and a manufacture thereof and of a circuit board where solder balls are disposed on apertures with a small diameter formed in the substrate. SOLUTION: When solder balls 10 are mounted on a substrate 2, in which aperture parts 14 at one end of which an electrode film 5 is formed are formed, a solder paste 13 is first printed on the aperture parts 14, and this solder paste 13 is heated and melted. Consequently, a solder 15 in the solder paste 13 flows into the aperture parts 14 and fills these aperture parts 14 to connect with the electrode film 5. Subsequently, solder balls 10 are bonded with the solder 15 filled in the aperture parts 14. In this manufacture, since the solder paste 13 is heated and melted prior to bonding the solder balls 10, the aperture parts 14 can be positively filled with solder 15, even if a diameter dimension L2 of the aperture parts 14 is small. Therefore, sure electrical connection of the electrode film 5 and the solder ball 10 is made.

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