专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPS6325540B2 失效
公开(公告)号：JPS6325540B2
公开(公告)日：1988-05-25
申请号：JP8791283
申请日：1983-05-19
申请人： FUJITSU LTD
发明人： CHIBA MASATERU , MIKAMI TAKU
IPC分类号： H04B1/10 , H03G3/34

2. 发明专利

JPS61201521A DECODING CIRCUIT FOR SPLIT PHASE SIGNAL 失效
公开(公告)号：JPS61201521A
公开(公告)日：1986-09-06
申请号：JP4210185
申请日：1985-03-04
申请人： FUJITSU LTD
发明人： NIIYAMA MANABU , MIKAMI TAKU
IPC分类号： H03M1/24 , H03M5/02 , H03M5/12 , H04L25/49
摘要： PURPOSE:To reduce remarkably bit error rate due to jitter by excluding all jitter range produced in a split phase signal from an integration range as much as possible. CONSTITUTION:An excluding signal generating circuit 3 consists of an integration range setting circuit 5 in response to a reproducing clock and an integration intermittent range setting circuit 6. The integration range setting circuit 5 is constituted so that the time from the end point of time of jitter range caused at a polarity inverting point between adjacent bits of a split phase signal until the start point of time of a jitter range caused at a polarity inversion point between adjacent bits appearing next on a time axis at the polarity inverting point of certain adjacent bits is set on after another in the polarity inverting point string between adjacent bits. The integration interruption range setting circuit 6 is constituted that the time of jitter range caused in the polarity inverting point in the bit of the split phase signal is set one after another in the polarity inverting point string of the bits.

3. 发明专利

JPS6090449A SELF-SYNCHRONIZING SCRAMBLE AND DESCRAMBLE SYSTEM 失效
公开(公告)号：JPS6090449A
公开(公告)日：1985-05-21
申请号：JP19861183
申请日：1983-10-24
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , OKA NOBUYUKI , MIKAMI TAKU , YABE TOSHIHIRO
IPC分类号： H04L9/12 , H04L9/22 , H04L25/03
摘要： PURPOSE:To increase selectable scramble patterns by using the parallel output of a shift register as an address to supply the output read out of a memory to one side of an exclusive OR circuit. CONSTITUTION:An input signal di is supplied to the output of a memory 12 as well as to the input of an exclusive OR circuit EXOR14. The output of the circuit 14 is supplied to a shift register 10, and the parallel output of the register 10 is supplied to the memory 12 in the form of an address. The output read out of the memory 12 is fed back to the EXOR14, and the output of the EXOR14 is sent to a transmission line. A memory 13 equivalent to the memory of the transmission side is used also for a descramble circuit at the reception side.

4. 发明专利

JPH0369457B2 失效
公开(公告)号：JPH0369457B2
公开(公告)日：1991-11-01
申请号：JP5940185
申请日：1985-03-26
申请人： FUJITSU LTD
发明人： TODA YOSHIFUMI , MIKAMI TAKU
IPC分类号： H04B7/26 , H04L27/00

5. 发明专利

JPH01202673A MOMENTARY INTERRUPTION DETECTING CIRCUIT 失效
公开(公告)号：JPH01202673A
公开(公告)日：1989-08-15
申请号：JP2557188
申请日：1988-02-08
申请人： FUJITSU LTD
发明人： SAKATA MINORU , MIKAMI TAKU
IPC分类号： G01R31/00 , G06F1/00 , G06F1/28 , H02H3/24
摘要： PURPOSE:To discriminate between the long-time interruption of a power supply and momentary interruption, by detecting that the voltage of a power supply drops to below a predetermined level to output a power-ON reset signal and judging the interruption of the power source when said voltage drop continues for a predetermined time. CONSTITUTION:The Q-output of a DFF circuit 30 rises when the output of a power source voltage comparing circuit (consisting of an operational amplifier or the like) is held at an L-level for the predetermined time clocked by a timer IC 20. This Q-output is applied to a microcomputer 4 as a power supply interruption signal. When the microcomputer 4 receives a power-ON reset POR signal (the output of an inverter 31), said microcomputer 4 holds the data immediately before the reception of said POR signal to an internal register to wait the recovery of the voltage of a power source and, when the microcomputer 4 receives H-level output from the circuit 30 after the elapse of the previous predetermined time, said microcomputer 4 judges the interruption of the power source to interrupt the processing operation continued up to the reception time of the POR signal. When the H-level signal (power supply interruption signal) is not received before the elapse of the predetermined time, the microcomputer 4 judges momentary interruption and sets the data immediately before the reception of the POR signal held to the register to an initial value to reopen processing operation.

6. 发明专利

JPS61173170A FREQUENCY DISCRIMINATION CIRCUIT 失效
公开(公告)号：JPS61173170A
公开(公告)日：1986-08-04
申请号：JP1471085
申请日：1985-01-29
申请人： FUJITSU LTD
发明人： SATO YUICHI , MIKAMI TAKU
IPC分类号： G01R23/15
摘要： PURPOSE:To permit the easy discrimination of a frequency of a monitor signal even if said frequency changes by discriminating whether an input signal is in the prescribed frequency range or not according to the presence or absence of an output pulse from a one-shot multicounter when a pulse is outputted from a reference time generating circuit. CONSTITUTION:The frequency and frequency range of the monitor signal from a master station are assumed to be 6,000+ or -15Hz. 5985 Is preset in a counter 10 and 30 is preset in the one-shot multicounter 11 from a discrimination frequency and discrimination frequency range setting part 13 by a CPU instruction. The pulses are emitted from the reference time generating circuit 14 at about 250 millisecond intervals from before the time when the counter 10 starts counting. Then when the 6,000+ or -15Hz monitor signal is inputted to the counter 10, the counter emits an output pulse upon counting of l496. A counter 11 emits the pulse of the width corresponding to the count value at the point of this time and inputs the pulse to an FF12. The pulses of 1-second intervals are emitted from the circuit 14 to the FF12 and a 1 level is outputted when the pulse inputted to the FF12 is stricken by by said pulse. The discrimination of the above-mentioned monitor signal is thus made possible.

7. 发明专利

JPS59214335A Squelch circuit 失效
标题翻译： SQUELCH电路
公开(公告)号：JPS59214335A
公开(公告)日：1984-12-04
申请号：JP8791283
申请日：1983-05-19
申请人： Fujitsu Ltd
发明人： CHIBA MASATERU , MIKAMI TAKU
IPC分类号： H04B1/10 , H03G3/34
CPC分类号： H03G3/341
摘要： PURPOSE:To stop completely the generation of a sound resulting from a receiver component in case of a break of a receive input level by turning off the speaker circuit of a mobile station in a time set shorter than the transmission time of an unmodulated carrier after the end of a telephone cell to be sent from a base station to the mobile station. CONSTITUTION:A counter COU is set at a falling point of an output waveform from a voice level detecting circuit V-DEF to operate the timer circuit included therein, and reset at rising point. Then this time circuit restarts at a break of voice output from an opponent station. A gate circuit G turns on a switch circuit SW only when the output of the counter COU and the output of a detector DET are both ''0'' and applied at the same time, and turns off it in other state. The switch circuit SW is turned off after the counter COU counts for a time T3, and a voice amplifier V-AMP and a speaker SP are disconnected from each other. Therefore, the circuit of the speaker SP is turned of before a noise component is outputted to the output side of the voice amplifier V-AMP.
摘要翻译：目的：通过在比未调制载波的传输时间短的时间内关闭移动台的扬声器电路，在发生接收输入电平中断的情况下完全停止由接收器部件产生的声音的产生要从基站发送到移动台的电话单元的结束。构成：将计数器COU设置在来自语音电平检测电路V-DEF的输出波形的下降点，以操作其中包括的定时器电路，并在上升点复位。然后，这个时间电路在对手站的语音输出断开时重新开始。只有当计数器COU的输出和检测器DET的输出都为“0”并且同时施加时，门电路G才接通开关电路SW，并且在其他状态下将其截止。在计数器COU计数一段时间T3之后，开关电路SW关闭，语音放大器V-AMP和扬声器SP彼此断开。因此，扬声器SP的电路在将声音分量输出到语音放大器V-AMP的输出侧之前转动。

8. 发明专利

JP2000151486A DIVERSITY RECEIVER AND ITS METHOD 失效
公开(公告)号：JP2000151486A
公开(公告)日：2000-05-30
申请号：JP31879398
申请日：1998-11-10
申请人： FUJITSU LTD
发明人： TOMIYOSHI TOKUO , MIKAMI TAKU , HAGA YOSHINOBU , YAMANO OSAMU
IPC分类号： H04J13/00 , H04B1/7117 , H04B7/08 , H04B7/26 , H04W16/28 , H04W28/18 , H04W88/02
摘要： PROBLEM TO BE SOLVED: To provide a configuration for a diversity reception circuit that requires only a small space and low current consumption. SOLUTION: An antenna changeover device 1 alternately selects a signal from an antenna A or B at a prescribed speed. The signal from the antenna A or B is given alternately to a radio reception section 2. The radio reception section 2 applies orthogonal detection to the signal received by the antennas A, B and gives the result to a branch selection section 4. The branch selection section 4 extracts either of the signal from the antennas A and B alternately placed temporally by an instruction of a searcher 7 and gives the extracted signal to a matched filter 6. The searcher 7 acquires an inverse spread timing from a correlation value and stores it to memories 12-1, 12-2. The searcher 7 acquires the inverse spread timing of a higher correlation value and gives it to an inverse spread section 3, where the signal is rake-received.

9. 发明专利

JPH0348697B2 失效
公开(公告)号：JPH0348697B2
公开(公告)日：1991-07-25
申请号：JP815386
申请日：1986-01-20
申请人： FUJITSU LTD
发明人： SATO JUICHI , MIKAMI TAKU
IPC分类号： H03L7/06

10. 发明专利

JPS63191433A BIT SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPS63191433A
公开(公告)日：1988-08-08
申请号：JP2390387
申请日：1987-02-04
申请人： FUJITSU LTD
发明人： MIKAMI TAKU
IPC分类号： H04L7/033 , H04L7/02 , H04L7/10
摘要： PURPOSE:To reduce accidents where data can not be received by converting input burst data in Manchester code into burst data in NRZ code by a decoder then turning off a gate means by a data discriminating means while a period from the detection of a frame pattern in this data to the end of the data. CONSTITUTION:The decoding means 7 converts the input data in Manchester code into the data in NRZ code and the data discriminating means 8 turns off the gate means 9 from the point where the frame pattern in the data is detected to the end of the data. Therefore, even if a phase comparing means 4 applies an H-level signal to the gate means 9 owing to temporary deterioration in the SN ratio of the input data, no edge detection signal is sent out to a D-PLL 6. Consequently, the possibility that a regenerated clock from the D-PLL is locked in wrong phase is improved and the possibility that the data can not be received is reduced.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式