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    • 2. 发明专利
    • WAITING REGULATING SYSTEM
    • JPS6084059A
    • 1985-05-13
    • JP9657883
    • 1983-05-31
    • FUJITSU LTDNIPPON TELEGRAPH & TELEPHONEOKI ELECTRIC IND CO LTDNIPPON ELECTRIC COHITACHI LTD
    • KOIKE TAKAYASUKINEMURA KAZUHIROSUOU MIKIOWATANABE TOSHIHIKOTSUKATANI TOSHIMICHI
    • H04M3/00H04M3/36
    • PURPOSE:To relieve succeeding regulating information by providing a means to wait regulating information disabled for registration, a means to renew the said information and a means to select the regulating information having high priority from the regulating information in waiting and registering it when the regulating information during registration is reliesed for registration. CONSTITUTION:If all tenant memories are occupied when a regulation logical circuit 8 forms regulation information (r) from congestion information (c), the circuit 8 forms waiting regulation information r' added with information representing degree of congestion from the information (r), stores the result to an idle standby tenant memory in a standby regulation information storage circuit 14, where the information is awaited. Moreover, the circuit 8 revises the information representing the degree of congestion in the information r' every time new information (c) relating to the information r' in standby is analyzed. When an occupied tenant memory is idle, the regulation logical control circuit 8 informs it to a waiting assigning order control circuit 13. The circuit 13 extracts sequentially the information r' in the waiting tenant memory, compares the information representing the degree of congestion, stores the information r' having the highest priority to a buffer 15 and the circuit 8 registers it to an idle tenant memory.
    • 3. 发明专利
    • Traffic data transferring system
    • 交通数据传输系统
    • JPS6120459A
    • 1986-01-29
    • JP14054684
    • 1984-07-09
    • Fujitsu LtdHitachi LtdNec CorpNippon Telegr & Teleph Corp Oki Electric Ind Co Ltd
    • AMAUCHI MAKOTOOKA MASAHIDEMANBA HIROSHIANDOU MOTOYUKIKOIKE TAKAYASU
    • H04M3/36
    • PURPOSE: To facilitate effective utilization of resource and processing such as conversion and summarizing of code in receiving processes by setting identifier information of data length and kind of data in the data when transmitting and receiving data of different kinds of data and different data length.
      CONSTITUTION: In data transferring of different transferring conditions, a transmitting side sets data length information 12 that indicates data length, a data category identifier 13 that indicates the kind of traffic data and data length information 14 that indicates the data length of each kind of data in the transferred data, and transfers from an observing device 3 to an interface device 9. The receiving side unifies receiving processes of traffic data of different data length by determining the receiving buffer size from information of data length 12. When converting the code of received data, the converting process is made efficient by information of the data category identifier 13 and data length 14.
      COPYRIGHT: (C)1986,JPO&Japio
    • 目的:通过在发送和接收不同类型的数据和不同数据长度的数据时,通过设置数据的数据长度和数据类型的标识符信息来促进资源和处理的有效利用,如转换和汇总接收过程中的代码。 构成:在不同传送条件的数据传送中,发送方设定指示数据长度的数据长度信息12,指示业务数据种类的数据类别标识符13和表示各种数据的数据长度的数据长度信息14 在传送的数据中,从观察设备3传送到接口设备9.接收侧通过从数据长度12的信息确定接收缓冲器大小来统一不同数据长度的业务数据的接收处理。当转换接收到的数据 数据,通过数据类别标识符13和数据长度14的信息使转换处理有效。
    • 8. 发明专利
    • EQUIVALENT REPRODUCTION SYSTEM OF SYSTEM LOAD
    • JPS59121447A
    • 1984-07-13
    • JP22453382
    • 1982-12-21
    • FUJITSU LTD
    • KOIKE TAKAYASUITOU MASAHIRO
    • G06F11/28G06F11/22G06F11/36
    • PURPOSE:To improve the performance of a test for confirmation and to reduce the labor for reproduction of load by reproducing automatically with high fidelity the load applied in a debugging process. CONSTITUTION:A system load reproducing device 3 is connected to a processor 1 which tests a real time processing program, i.e., a test object. Then a test object processing mechanism 11 is provided to the processor 1 to set and execute a processing prorgram. While a collected point memory circuit 31 which stores previously a desired collected point data i1 is provided to the device 3. The necessary load information is supplied to the mechanism 11 by means of an input/output handler 12 of the processor 1, and an executing address i2 is applied to an address matching circuit 32. The address i2 is collated with the data i1 of the circuit 31 and then processed by a transaction collection control circuit 33, a timing control circuit 35, a transaction memory control circuit 36, etc. Thus the load applied in a debug working process is reproduced automatically with high fidelity. With this load reproduction, the performance is improved for test for confirmation. Furthermore the labor for reproduction is reduced.