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1. 发明专利

JP2007027743A Integrated semiconductor structure and manufacturing method thereof 审中-公开
标题翻译：一体化半导体结构及其制造方法
公开(公告)号：JP2007027743A
公开(公告)日：2007-02-01
申请号：JP2006192767
申请日：2006-07-13
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： GOLDBACH MATTHIAS , WU DONGPING
IPC分类号： H01L21/8234 , H01L21/283 , H01L21/8238 , H01L21/8242 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/49
CPC分类号： H01L21/823857
摘要： PROBLEM TO BE SOLVED: To provide an integrated semiconductor structure capable of adjusting the Fermi level of a P-MOS appropriately.
SOLUTION: A first transistor region T1 is an n-MOS region, a second transistor region T2 is a p-FET region, a base part dielectric layer 2 made of SiO
2 is formed on the first and second transistor regions, and an N+ polysilicon gate 4 is formed on the dielectric layer 2. The first region is protected by a mask, an aluminum ion is injected, and heat treatment is performed, thus forming a high-dielectric-constant interface dielectric layer 3 of AlxOv between the gate dielectric layer 2 and the N+ polysilicon gate 4, strengthening Fermi pinning effect, and hence adjusting a work function of the P-MOS of N+ polysilicon to a value close to the function of a P+ polysilicon gate.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够适当地调整P-MOS的费米能级的集成半导体结构。解决方案：第一晶体管区域T1是n-MOS区域，第二晶体管区域T2是p-FET区域，由SiO 2制成的基极介质层2形成在第一和第二晶体管区域，并且在电介质层2上形成N +多晶硅栅极4.第一区域被掩模保护，注入铝离子并进行热处理，从而形成高介电常数界面在栅极电介质层2和N +多晶硅栅极4之间的Al x O v的介电层3，强化费米钉扎效应，并因此将N +多晶硅的P-MOS的功函数调整到接近P +多晶硅栅极功能的值。版权所有（C）2007，JPO＆INPIT

2. 发明专利

JP2007184578A Atomic layer deposition process 审中-公开
标题翻译：原子层沉积过程
公开(公告)号：JP2007184578A
公开(公告)日：2007-07-19
申请号：JP2006338407
申请日：2006-12-15
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： ERBEN ELKE , JAKSCHIK STEFAN , KERSCH ALFRED , LINK ANGELA , SUNDQVIST JONAS
IPC分类号： H01L21/318
CPC分类号： C23C16/34 , C23C16/45525 , C23C16/45531 , H01L21/3141 , H01L21/318 , H01L28/40
摘要： PROBLEM TO BE SOLVED: To provide an atomic layer deposition process capable of forming a uniform layer on a substrate.
SOLUTION: The atomic layer deposition process to form the uniform layer on the substrate comprises the steps of carrying the substrate in a reaction chamber; forming an intermediate product by introducing a first precursor into the reaction chamber, and by reacting the first precursor on a front surface of the substrate; forming a primary product by introducing a second precursor having a first sticking coefficient into the reaction chamber, and by reacting the second precursor with a part of the intermediate product; forming a secondary product by introducing a third precursor having a large sticking coefficient into the reaction chamber, and by reacting the third precursor with a remaining part of the intermediate product; and reducing an effective sticking coefficient of the third precursor by the second precursor and the primary product of the second precursor which partially cover the surface.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够在基板上形成均匀层的原子层沉积工艺。解决方案：在衬底上形成均匀层的原子层沉积工艺包括以下步骤：在反应室内承载衬底; 通过将第一前体引入所述反应室中并通过使所述第一前体在所述基板的前表面上反应而形成中间产物; 通过将具有第一粘附系数的第二前体引入反应室中，并使第二前体与中间产物的一部分反应形成初级产物; 通过将具有大粘附系数的第三前体引入反应室，并通过使第三前体与中间产物的剩余部分反应形成二次产物; 并且通过第二前体和部分地覆盖表面的第二前体的初级产物降低第三前体的有效粘附系数。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2007052903A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2007052903A
公开(公告)日：2007-03-01
申请号：JP2006219255
申请日：2006-08-11
申请人： Nanya Technology Corp , Qimonda Ag , キマンダアーゲーQimonda AG , ナンヤテクノロジーコーポレーション
发明人： RAINER BARTENSCHLAGER , LEE WEN-MING , MUN JIN-SUK , SCHNABEL FLORIAN , CHRISTIAN SICHERT
IPC分类号： G11C11/408 , G11C11/409 , H01L21/8242 , H01L27/108
CPC分类号： G11C7/04 , G11C11/4074 , G11C11/4076 , G11C11/4094
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can be operated at a high speed over a wide temperature range, and to provide a method for operating the semiconductor device so that a semiconductor memory device may not be influenced by variation of temperature.
SOLUTION: In this invention, the semiconductor memory device comprises a temperature dependent voltage source for outputting a voltage at its output dependent on a risen temperature measured on the semiconductor memory device. At least one memory cell is provided with at least one first transistor, and the first transistor includes a first transistor main body. The first transistor main body is connected to the output of the temperature dependent voltage source.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种可在宽温度范围内高速运转的半导体器件，并提供一种操作半导体器件的方法，使得半导体存储器件不会受到变化的影响温度。解决方案：在本发明中，半导体存储器件包括一个依赖于温度的电压源，用于根据在半导体存储器件上测得的上升温度在其输出端输出电压。至少一个存储单元设置有至少一个第一晶体管，并且第一晶体管包括第一晶体管主体。第一晶体管主体连接到与温度相关的电压源的输出端。版权所有（C）2007，JPO＆INPIT

4. 发明专利

JP2009124137A Method for forming integrated circuit device and corresponding integrated circuit device 审中-公开
标题翻译：形成集成电路设备和相关集成电路设备的方法
公开(公告)号：JP2009124137A
公开(公告)日：2009-06-04
申请号：JP2008275804
申请日：2008-10-27
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： BOSHOLM OLE , LEPPER MARCO , SPRINGER GOETZ , WEBER DETLEF , BONSDORF GRIT , PIETZSCHMANN FRANK
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/5258 , H01L21/31144 , H01L21/3148 , H01L21/3185 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a method for forming an integrated circuit device and a corresponding integrated circuit device. SOLUTION: The method for forming an integrated circuit device comprises steps of: forming a first level on a substrate; forming a second level above the first level; forming a cap layer on the second level which covers a first region of the second level and leaves a second region uncovered; and simultaneously etching a first contact hole in the first region and a second contact hole in the second region so that etching is selective to the cap layer in the second region and proceeds to a greater depth in the first region. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于形成集成电路器件和相应的集成电路器件的方法。解决方案：用于形成集成电路器件的方法包括以下步骤：在衬底上形成第一电平; 形成第一级以上的第二级; 在所述第二层上形成覆盖所述第二层的第一区域并使未覆盖的第二区域的盖层; 同时蚀刻第一区域中的第一接触孔和第二区域中的第二接触孔，使得蚀刻对第二区域中的覆盖层具有选择性，并且在第一区域中进一步增加深度。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2008066724A Integrated memory cell array 审中-公开
标题翻译：集成存储单元阵列
公开(公告)号：JP2008066724A
公开(公告)日：2008-03-21
申请号：JP2007225756
申请日：2007-08-31
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： WEIS ROLF
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L29/66621 , H01L27/10876 , H01L27/10882 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an integrated memory cell array such as a DRAM having an improved joint leak. SOLUTION: An integrated memory cell array includes a semiconductor substrate 1 and a plurality of cell transistor devices. The cell transistor device includes a pillar 1a formed on a substrate 1; a gate trench for surrounding the pillar; first source/drain regions S formed on an upper region of the pillar; a gate insulating body 40 formed at the bottom of the gate trench for surrounding a lower region of the pillar; a gate 50 for surrounding the lower region of the pillar formed in a gate insulating body in the gate trench for surrounding the lower region of the pillar; and second source/drain regions D1 and D2 formed in the upper region of the semiconductor substrate adjacent to the gate trench. The cell transistor device further includes a plurality of bit lines BL, a plurality of word lines WL, and a plurality of cell capacitors connected to source/drain regions of the cell transistor device. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有改进的接头泄漏的诸如DRAM的集成存储单元阵列。解决方案：集成存储单元阵列包括半导体衬底1和多个单元晶体管器件。单元晶体管器件包括形成在基板1上的柱1a; 用于围绕柱的门沟; 形成在柱的上部区域上的第一源极/漏极区域S; 栅极绝缘体40，形成在栅极沟槽的底部，用于围绕柱的下部区域; 用于围绕形成在栅极沟槽中的栅极绝缘体中的柱的下部区域的栅极50，用于围绕柱的下部区域; 以及形成在与栅极沟槽相邻的半导体衬底的上部区域中的第二源极/漏极区域D1和D2。单元晶体管器件还包括连接到单元晶体管器件的源/漏区的多个位线BL，多个字线WL和多个单元电容器。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007103920A Semiconductor memory device and manufacturing method thereof 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：JP2007103920A
公开(公告)日：2007-04-19
申请号：JP2006232929
申请日：2006-08-30
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： MUELLER THORSTEN , STEFANO PARASCANDOLA , OLLIGS DOMINIK , RIEDEL STEPHAN , KNOEFLER ROMAN , CASPARY DIRK
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： PROBLEM TO BE SOLVED: To provide a method of suitably forming contacts on buried bit lines. SOLUTION: Bit lines (10) are formed by implanting dopants by means of a sacrificial hard mask layer. The hard mask layer is later replaced with gate electrodes made of polysilicon in a memory cell array. Striplike areas of the memory cell array extending transversely across the bit lines are reserved by a blocking layer (11) to be occupied by bit line contacts. In these areas, the hard mask (5) is used to form contact holes (13) which are self-aligned with the implanted buried bit lines. Between the blocked areas, word lines are arranged perpendicular to the bit lines. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种在掩埋位线上适当地形成接触的方法。解决方案：通过牺牲硬掩模层注入掺杂剂形成位线（10）。硬掩模层随后由存储单元阵列中由多晶硅制成的栅电极代替。跨越位线横向延伸的存储单元阵列的带状区域由阻挡层（11）保留以被位线接触占据。在这些区域中，硬掩模（5）用于形成与注入的掩埋位线自对准的接触孔（13）。在阻塞区域之间，字线垂直于位线布置。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007043154A Method of manufacturing semiconductor structure having wafer through-contact and corresponding semiconductor structure 审中-公开
标题翻译：制造具有通过接触的波形和相应半导体结构的半导体结构的方法
公开(公告)号：JP2007043154A
公开(公告)日：2007-02-15
申请号：JP2006206645
申请日：2006-07-28
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： HEDLER HARRY , IRSIGLER ROLAND
IPC分类号： H01L21/3205 , H01L23/52
CPC分类号： H01L21/76898
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor structure having a wafer through-contact that can be achieved easily and safely.
SOLUTION: The method of manufacturing a semiconductor structure having a wafer through-contact comprises: a step of providing a semiconductor wafer (1) having a bulk region (1a) and an active region (1b); a step of forming multiple contact trenches (5a-5f), which extend from the top surface (0) of the active region (1b) to the bulk region (1a), in the semiconductor wafer (1); a step of forming a first dielectric isolation layer (8) on the sidewalls and the bottoms of the contact trenches (5a-5f); a step of providing a first conductive filler (10) in the multiple contact trenches (5a-5f); a step of forming a via (V) that is arranged in the semiconductor wafer (1), extends from the backside (B) of the bulk region (1a) to the multiple contact trenches (5a-5f), and exposes the conductive filler (10); a step of forming a second dielectric isolation layer (15) on the sidewall of the via (V); and a step of providing a second conductive filler (20) in the via (V) which comes into contact with the exposed conductive filler (10).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造具有可以容易且安全地实现的晶片通过接触的半导体结构的方法。解决方案：制造具有晶片贯通接触的半导体结构的方法包括：提供具有体区（1a）和有源区（1b）的半导体晶片（1）的步骤; 在半导体晶片（1）中形成从有源区（1b）的顶表面（0）延伸到体区（1a）的多个接触沟槽（5a-5f）的步骤; 在所述接触沟槽（5a-5f）的侧壁和底部上形成第一介电隔离层（8）的步骤; 在多个接触沟槽（5a-5f）中设置第一导电填料（10）的步骤; 形成布置在半导体晶片（1）中的通孔（V）的步骤从主体区域（1a）的背面（B）延伸到多个接触沟槽（5a-5f），并将导电填料（10）; 在所述通孔（V）的侧壁上形成第二介电隔离层（15）的步骤; 以及在与暴露的导电填料（10）接触的通孔（V）中提供第二导电填料（20）的步骤。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2007036256A Non-volatile resistance memory cell based on metallic oxide nanoparticle, method for manufacturing same and arrangement of memory cell 审中-公开
标题翻译：基于金属氧化物纳米粒子的非易失性存储单元，其制造方法和存储单元布置
公开(公告)号：JP2007036256A
公开(公告)日：2007-02-08
申请号：JP2006203266
申请日：2006-07-26
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： UFERT KLAUS-DIETER
IPC分类号： H01L27/10
CPC分类号： B82Y30/00 , B82Y10/00 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/1608
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile resistance memory cell based on metallic oxide nanoparticles, a method for manufacturing the same, and the arrangement of the memory cell.
SOLUTION: The non-volatile memory including a first conductive electrode area, a second conductive electrode area and a memory area arranged between the first and second conductive electrode areas is disclosed. The memory area contains one or more metallic oxide nanoparticles, the metallic oxide nanoparticle is brought into contact with and electrically connected to the first and second electrode area through a contact position, and when external voltage is applied, the metallic oxide nanoparticle displays a bistable resistance characteristic.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种基于金属氧化物纳米颗粒的非易失性电阻存储单元，其制造方法和存储单元的布置。公开了包括第一导电电极区域，第二导电电极区域和布置在第一和第二导电电极区域之间的存储区域的非易失性存储器。存储区域包含一种或多种金属氧化物纳米颗粒，金属氧化物纳米颗粒通过接触位置与第一和第二电极区域接触并电连接，并且当施加外部电压时，金属氧化物纳米颗粒显示双稳态电阻特性。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2008258623A Zirconium oxide capacitor and manufacturing method therefor 审中-公开
标题翻译：氧化锆氧化锆电容器及其制造方法
公开(公告)号：JP2008258623A
公开(公告)日：2008-10-23
申请号：JP2008091780
申请日：2008-03-31
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： BOESCKE TIM , SCHROEDER UWE
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01G4/1236 , H01G4/33 , H01L28/40 , Y10T29/417
摘要： PROBLEM TO BE SOLVED: To provide a capacitor structure which contains an zirconium oxide and a dopant oxide. SOLUTION: The capacitor structure includes a first electrode 100 and a second electrode 120, between which a dielectric film consisting of a deposit of atomic layers is disposed, the dielectric film including a zirconium oxide 102 and a dopant oxide. The dopant has an ion radius different from that of the zirconium by 24 pm or more, and the dielectric film includes a dielectric film material containing an additive element of 10 atomic percentage or less when oxygen is excluded. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种包含氧化锆和掺杂剂氧化物的电容器结构。电容器结构包括第一电极100和第二电极120，在该第一电极100和第二电极120之间设置由原子层沉积构成的电介质膜，该电介质膜包括氧化锆102和掺杂剂氧化物。该掺杂剂的离子半径与锆的离子半径不同于24μm或更大，并且当排除氧时，电介质膜包括含有10原子百分比或更小的添加元素的电介质膜材料。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2008113005A Method of manufacturing integrated semiconductor structure 审中-公开
标题翻译：制造集成半导体结构的方法
公开(公告)号：JP2008113005A
公开(公告)日：2008-05-15
申请号：JP2007278806
申请日：2007-10-26
申请人： Qimonda Ag , キマンダアーゲーQimonda AG
发明人： SCHLOSSER TILL
IPC分类号： H01L21/8242 , H01L21/283 , H01L21/3205 , H01L27/108
CPC分类号： H01L27/10894 , H01L27/10882 , H01L27/10891
摘要： PROBLEM TO BE SOLVED: To provide a reliable manufacturing process which can form a cell array of a memory device and surrounding components in quantities, at the same time, and safely.
SOLUTION: An integrated semiconductor structure manufacturing method and an integrated semiconductor structure corresponding to it are provided. The method, which is a step of forming a surrounding circuit in a surrounding device area, includes a step that the surrounding circuit is at least partly formed on a semiconductor substrate and has a surrounding transistor having a first gate dielectric formed in a first high temperature treatment step and a step that a plurality of memory cells are formed in one memory cell area. Each memory cell is at least partly formed on the semiconductor substrate, has a second gate dielectric formed in the second high temperature treatment step, and has an access transistor having a metal gate conductor. The first and second high temperature treatment steps are performed before a step of forming a metal gate conductor.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供可靠的制造过程，其可以同时且安全地在数量上形成存储器件的单元阵列和周围的元件。解决方案：提供了一种集成半导体结构制造方法和与之对应的集成半导体结构。作为在周围设备区域中形成周围电路的步骤的方法包括以下步骤：周围电路至少部分地形成在半导体衬底上，并且具有围绕晶体管，其具有在第一高温下形成的第一栅极电介质处理步骤和在一个存储单元区域中形成多个存储单元的步骤。每个存储单元至少部分地形成在半导体衬底上，具有在第二高温处理步骤中形成的第二栅极电介质，并具有具有金属栅极导体的存取晶体管。第一和第二高温处理步骤在形成金属栅极导体的步骤之前进行。版权所有（C）2008，JPO＆INPIT

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