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1. 发明公开

EP4059143A1 VITERBI DECODING FOR TRELLIS CODED MODULATION USED IN STORAGE SYSTEMS HAVING NON-GAUSSIAN OUTPUTS 审中-实审
公开(公告)号：EP4059143A1
公开(公告)日：2022-09-21
申请号：EP20816330.3
申请日：2020-11-05
申请人： Microsoft Technology Licensing, LLC
发明人： WEATHERS, Anthony D. , NEMATI, Majid Anaraki , ZIPEROVICH, Pablo A.
IPC分类号： H03M13/41 , H03M13/25 , G06F11/00 , H03M13/11 , H03M13/27

2. 发明公开

EP3719802A1 DECODING DEVICE AND DECODING METHOD 无效
公开(公告)号：EP3719802A1
公开(公告)日：2020-10-07
申请号：EP18880513.9
申请日：2018-10-11
申请人： Sony Semiconductor Solutions Corporation
发明人： SHIRAISHI, Junya
IPC分类号： G11B20/14 , G11B20/18 , H03M13/41 , H04L25/497
摘要： Deterioration of convergence performance or operational stability due to an increase in constraint length is suppressed when coefficients are updated, so that decoding performance is improved.
A decoding device according to the present technology includes an adaptive equalization unit that performs adaptive equalization, an adaptive maximum likelihood decoding unit that causes an identification point of maximum likelihood decoding to adaptively follow a characteristic of an input signal, a target waveform generation unit that, by convoluting a partial response coefficient into a decoded value, generates an equalization target waveform of the adaptive equalization which is performed by the adaptive equalization unit, an error signal generation unit that generates, as an equalization error signal, an error signal between the equalization target waveform and an equalized signal, and a coefficient updating unit that, through least-square-method computation for minimizing a correlation between the decoded value and the equalization error signal, updates the partial response coefficient which is used by the target waveform generation unit to generate the equalization target waveform.

3. 发明授权

EP3281319B1 DECODING OF MESSAGES WITH KNOWN OR HYPOTHESIZED DIFFERENCE 有权
公开(公告)号：EP3281319B1
公开(公告)日：2020-03-25
申请号：EP16714867.5
申请日：2016-04-05
申请人： Telefonaktiebolaget LM Ericsson (publ)
发明人： AXMON, Joakim , LINDOFF, Bengt , WALLÉN, Anders
IPC分类号： H04L1/00 , H03M13/41 , H04L1/08

4. 发明授权

EP2619673B1 MEMORY QUALITY MONITOR BASED COMPENSATION METHOD AND APPARATUS 有权
公开(公告)号：EP2619673B1
公开(公告)日：2019-05-22
申请号：EP11827202.0
申请日：2011-09-08
申请人： Micron Technology, Inc.
发明人： LIIKANEN, Bruce, A. , CADLONI, Gerald, L. , KOUDELE, Larry, J. , SEABURY, John, L. , VAN AKEN, Stephen, P. , WAGNER, Guy, R.
IPC分类号： G11C16/34 , G11C11/56 , G11C13/00 , G11C7/10 , G06F11/08 , G06F11/10 , H03M13/11 , H03M13/15 , H03M13/37 , H03M13/41

5. 发明公开

EP3468049A1 SIGNAL PROCESSING DEVICE AND SIGNAL PROCESSING METHOD 有权转让
公开(公告)号：EP3468049A1
公开(公告)日：2019-04-10
申请号：EP17802596.1
申请日：2017-05-12
申请人： Sony Corporation
发明人： HIGASHINO, Satoru
IPC分类号： H03M13/41 , G11B20/10 , G11B20/14 , G11B20/18
摘要： The present technology relates to a signal processing apparatus and a signal processing method capable of allowing data recorded at a high density to be robustly reproduced.
A frame sync (FS) is restored by performing maximum likelihood decoding of the FS according to a time-varying trellis with a state and a state transition being limited according to a time, in maximum likelihood decoding of a reproduction signal reproduced from a disk-shaped recording medium, the FS representing a head of a frame, the FS of the frame being arranged at the head of the frame, the FS being recorded at the same positions in a track direction in two adjacent tracks.

6. 发明授权

EP2661815B1 PROCÉDÉ DE CORRECTION DE MESSAGES CONTENANT DES BITS DE BOURRAGE 有权
公开(公告)号：EP2661815B1
公开(公告)日：2018-11-14
申请号：EP12700017.2
申请日：2012-01-03
申请人： Centre National d'Etudes Spatiales
发明人： PREVOST, Raoul , BONACCI, David , COULON, Martial , TOURNERET, Jean-Yves , LE MAITRE, Julia , MILLERIOUX, Jean-Pierre
IPC分类号： H03M13/39 , H03M13/41
CPC分类号： H03M13/256 , H03M13/3994 , H03M13/41 , H03M13/4146 , H03M13/6508

7. 发明授权

EP3058463B1 PARALLEL DYNAMIC PROGRAMMING THROUGH RANK CONVERGENCE 失效
公开(公告)号：EP3058463B1
公开(公告)日：2018-08-22
申请号：EP14793927.6
申请日：2014-10-13
申请人： Microsoft Technology Licensing, LLC
发明人： MYTKOWICZ, Todd D. , MUSUVATHI, Madanlal , MALEKI, Saeed
IPC分类号： G06F9/50 , G06F17/11 , G06K9/62 , H03M13/00 , H03M13/41
CPC分类号： G06F8/22 , G06F8/456 , G06F9/5066 , G06F17/11 , G06K9/00 , G06K9/6203 , G06Q10/04 , H03M13/41 , H03M13/6561
摘要： The techniques and/or systems described herein implement parallel processing of a dynamic programming problem across stages and/or clusters by breaking dependencies between stages and/or clusters. For instance, the techniques and/or systems may identify dependencies between sub-problems of the dynamic programming problem and group the sub-problems into stages. The techniques and/or systems may also group the stages into clusters (e.g., at least two clusters to be parallel processed). Then, the techniques and/or systems generate one or more solutions to use instead of actual solutions so that the dynamic programming problem can be parallel processed across stages and/or clusters.

8. 发明授权

EP2833360B9 DECODING DEVICE AND DECODING METHOD 有权
公开(公告)号：EP2833360B9
公开(公告)日：2018-04-25
申请号：EP13769315.6
申请日：2013-03-28
申请人： Panasonic Intellectual Property Management Co., Ltd.
发明人： NAKATA, Kohei , HINO, Yasumori , TAKAGI, Yuji , NAKASENDO, Tsuyoshi
IPC分类号： G11B20/18 , G11B20/14 , H03M13/41 , H04L1/00
CPC分类号： G11B20/10 , G11B7/005 , G11B20/10277 , H03M13/1105 , H03M13/1515 , H03M13/41 , H03M13/6331 , H04L1/004
摘要： A decoding device includes: an interference canceling circuit (104) which extracts, from states of 2 K -number (where K is a natural number) of detected signals that are likely within a range of K bit width where an interference between bits of the digital information occurs due to predetermined frequency characteristics, most likely 2 M -number (where M is a natural number) of detected signals respectively corresponding to states of 2 M -number of detected signals which exist within a range of M bit width that is included in the range of K bit width; and a Viterbi decoding circuit (105) which generates a decoded signal by calculating differences between the 2 M -number of detected signals extracted by the interference canceling circuit (104) and expectation signals respectively corresponding to the 2 M -number of detected signals and also by selecting a transition sequence of a state of a detected signal for which the calculated difference is smallest.

9. 发明授权

EP2346174B1 SOFT DECISION ENHANCEMENT 有权
标题翻译：软决策增强
公开(公告)号：EP2346174B1
公开(公告)日：2017-12-13
申请号：EP11163674.2
申请日：2005-08-05
申请人： MStar Software R&D (Shenzhen) Ltd. , MStar Semiconductor, Inc. , MStar Semiconductor, Inc. , MStar France SAS
发明人： Fatemi-Ghomi, Navid , Valadon, Cyril
IPC分类号： H03M13/41 , H04L1/00 , H04L27/22
CPC分类号： H04L1/0059 , H03M13/3955 , H03M13/4138 , H04L1/0054
摘要： A Viterbi trellis processing technique in which soft decisions and hard decisions are derived from a received signal and the soft decisions are enhanced by being modified using the hard decisions. A log likelihood ratio for a bit of the received signal can be derived by grouping candidate metrics associated with the decision that the bit has a first state, grouping candidate metrics associated with the decision that the bit has a second state, applying respective functions to the groups and calculating the difference of the function values.

10. 发明公开

EP2672628A4 METHOD AND APPARATUS FOR DECODING AND CHECKING TAIL-BITING CONVOLUTIONAL CODE 审中-公开
公开(公告)号：EP2672628A4
公开(公告)日：2017-11-22
申请号：EP11857479
申请日：2011-09-22
申请人： ZTE CORP
发明人： GONG MING
IPC分类号： H03M13/23 , H03M13/09 , H03M13/41 , H04L1/00
CPC分类号： H03M13/23 , H03M13/09 , H03M13/413 , H03M13/6525 , H04L1/0054 , H04L1/0059 , H04L1/0061 , H04L1/0071
摘要： The disclosure discloses a method and apparatus for decoding and checking a tail-biting convolutional code, so as to solve the problem of reducing a processing time delay in decoding and checking the tail-biting convolutional code in the prior art. The disclosure fully utilizes structural features of the tail-biting convolutional code to re-sort Log-Likelihood Ratio (LLR) values input into a decoder, and by reconstructing a derivative generator polynomial of a convolutional code, allows the decoder to output in serial according to a normal ordering of information bits during backtracking, that is, a first bit of an information sequence is first decoded successfully. Thus, CRC checking may be activated as soon as possible, so that part of the backtracking process and the CRC checking may be performed in parallel, thereby achieving the objective of reducing a processing time delay in decoding and checking the tail-biting convolutional code. The disclosure does not increase any hardware expense, belongs to an improvement of low cost, and does not cause any decoding performance downgrade.

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