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2. 发明公开

EP4423914A1 NUMÉRISEUR RADIOFRÉQUENCE À DYNAMIQUE AUGMENTÉE 审中-实审
公开(公告)号：EP4423914A1
公开(公告)日：2024-09-04
申请号：EP22805883.0
申请日：2022-10-25
申请人： Thales , Université de Bordeaux , Institut Polytechnique de Bordeaux , Centre National de la Recherche Scientifique
发明人： LAPORTE-FAURET, Baptiste , FUCHE, Loïc , MINGER, Bryce , FERRE, Guillaume , DALLET, Dominique
IPC分类号： H04B1/10 , H03M1/16 , H03M3/00 , H03M1/12
CPC分类号： H04B1/10 , H03M1/167 , H03M1/129 , H03M3/414 , H03M3/478

3. 发明公开

EP4178197A1 ANALOGUE TO DIGITAL CONVERTER FOR IMAGE SENSOR READOUT 审中-实审
公开(公告)号：EP4178197A1
公开(公告)日：2023-05-10
申请号：EP21206179.0
申请日：2021-11-03
申请人： Teledyne Innovaciones Microelectrónicas, SLU
发明人： SEGOVIA, Jose Angel , GONZALEZ MARQUEZ, Ana , DOMINGUEZ CASTRO, Rafael , CHARLET, Alexander , VILLEGAS, Alberto
IPC分类号： H04N5/357 , H04N5/355 , H03M3/00 , H03M1/16
摘要： An analogue to digital converter for converting the analogue output of a dual conversion gain pixel of an image sensor. The dual conversion gain pixel is operable to sequentially output a reset pixel value and a signal pixel value sequentially with both a first gain and a second gain different to the first gain. The analogue to digital converter comprises analogue storage for storing the reset pixel value output with the first gain. The analogue to digital converter further comprises a converter stage arranged to sequentially sample a first analogue input indicative of a reset pixel value of the dual conversion gain pixel and a second analogue input indicative of a signal pixel value of the dual conversion gain pixel. The converter stage is configured to sequentially sample the first input and the second input and output a digital value indicative of a difference between the first input and the second input. The analogue to digital converter further comprises circuitry configured to sequentially provide the reset pixel value output with the second gain as a first input to the converter stage and the signal pixel value output with the second gain as a second input to the converter stage such that the converter stage sequentially samples the first and second inputs and outputs a first digital value indicative of a difference between the reset pixel value output with the second gain and the signal pixel value output with the second gain. The circuitry is further configured to provide the reset pixel value output with the first gain and stored in the analogue storage as a first input to the converter stage and the signal pixel value output with the first gain as a second input to the converter stage wherein the converter stage is configured to sample the first and second inputs and output a differential signal indicative of a difference between the reset pixel value output with the first gain and the signal pixel value output with the first gain. An image sensor comprising the analogue to digital converter, a system comprising the image sensor and a method are also described herein.

4. 发明公开

EP4066380A1 SWITCHED-CAPACITOR AMPLIFIER AND PIPELINED ANALOG-TO-DIGITAL CONVERTER COMPRISING THE SAME 审中-实审
公开(公告)号：EP4066380A1
公开(公告)日：2022-10-05
申请号：EP20804589.8
申请日：2020-11-18
申请人： ams International AG
发明人： MICHEL, Fridolin
IPC分类号： H03F3/00 , H03M1/06 , H03M1/16 , H03M1/46 , G04F10/00 , H03M1/56

5. 发明公开

EP3840227A1 CONTINUOUS-TIME OVERSAMPLING PIPELINE ANALOG-TO-DIGITAL CONVERTER 审中-实审
公开(公告)号：EP3840227A1
公开(公告)日：2021-06-23
申请号：EP21151756.0
申请日：2014-03-03
申请人： Analog Devices International Unlimited Company
发明人： Shibata, Hajime
IPC分类号： H03M1/12 , H03M1/44 , H03M1/16
摘要： A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal.

6. 发明公开

EP3836403A1 MICROPROCESSOR-ASSISTED CALIBRATION FOR ANALOG-TO-DIGITAL CONVERTER 审中-实审
公开(公告)号：EP3836403A1
公开(公告)日：2021-06-16
申请号：EP20212305.5
申请日：2015-12-15
申请人： Analog Devices, Inc.
发明人： SPEIR, Carroll C. , OTTE, Eric , RAKULJIC, Nevena , BRAY, Jeffrey Paul
IPC分类号： H03M1/06 , H03M1/10 , H03M1/12 , H03M1/16
摘要： Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

7. 发明公开

EP3570436A1 MISMATCH AND REFERENCE COMMON-MODE OFFSET INSENSITIVE SINGLE-ENDED SWITCHED CAPACITOR GAIN STAGE WITH REDUCED CAPACITOR MISMATCH SENSITIVITY 有权
公开(公告)号：EP3570436A1
公开(公告)日：2019-11-20
申请号：EP19174769.0
申请日：2019-05-15
申请人： NXP USA, Inc.
发明人： Garrity, Douglas Alan , Hoseini, Mariam , Braswell, Brandt , Kabir, Mohammad Nizam
IPC分类号： H03F3/00 , H03F3/45 , H03M1/16
摘要： A switched-capacitor gain stage circuit (70) and method include an amplifier (71) connected to an input sampling circuit (73) with sampling switched capacitors (C1, C2) for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes (72) to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors (C3, C4) connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

8. 发明授权

EP2571169B1 A/D CONVERTER 有权
公开(公告)号：EP2571169B1
公开(公告)日：2019-07-03
申请号：EP11780708.1
申请日：2011-05-13
申请人： National University Corporation Shizuoka University
发明人： KAWAHITO Shoji
IPC分类号： H03M1/14 , H03M1/16 , H03M1/40 , H03M1/56 , H04N5/378 , H04N5/357

9. 发明公开

EP3490152A1 INTERLEAVING QUANTIZER IN CONTINUOUS-TIME DELTA-SIGMA MODULATOR FOR QUANTIZATION LEVEL INCREMENT 有权
公开(公告)号：EP3490152A1
公开(公告)日：2019-05-29
申请号：EP18202441.4
申请日：2018-10-24
申请人： MEDIATEK INC.
发明人： HSIEH, Hung-Yi
IPC分类号： H03M3/00 , H03M1/16 , H03M1/14
摘要： The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.

10. 发明公开

EP3465917A1 VERFAHREN ZUR ANALOG-DIGITAL-WANDLUNG UND UMSETZUNG ANALOGER EINGANGSSIGNALE 审中-公开
公开(公告)号：EP3465917A1
公开(公告)日：2019-04-10
申请号：EP17734632.7
申请日：2017-05-18
申请人： Küls, Guido Erwin , Greve, Anne Amanda
发明人： KÜLS, Guido Erwin
IPC分类号： H03M1/12 , H03M1/16

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