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1. 发明授权

EP3534268B1 MEMORY INTERFACE 有权
公开(公告)号：EP3534268B1
公开(公告)日：2023-08-23
申请号：EP19159831.7
申请日：2019-02-27
发明人： ROBINSON, Martin John , LANDERS, Mark
IPC分类号： G06F12/0831 , G06F12/0846 , G06F12/1018

2. 发明授权

EP3311281B1 ADDRESS TRANSLATION 有权
公开(公告)号：EP3311281B1
公开(公告)日：2019-05-22
申请号：EP16720505.3
申请日：2016-04-28
申请人： ARM Limited
发明人： PARKER, Jason , GRISENTHWAITE, Richard Roy , ROSE, Andrew Christopher
IPC分类号： G06F12/1036 , G06F12/14 , G06F12/1018 , G06F9/46 , G06F21/72 , G06F21/78

3. 发明公开

EP3977270A1 GRAPHICS CONTEXT BOUNCING 审中-实审
公开(公告)号：EP3977270A1
公开(公告)日：2022-04-06
申请号：EP20813774.5
申请日：2020-05-29
申请人： Advanced Micro Devices, Inc.
发明人： MCCRARY, Rex Eldon , LUO, Yi , WISE, Harry J. , ASHKAR, Alexander Fuad , MANTOR, Michael
IPC分类号： G06F9/38 , G06F9/48 , G06T1/20 , G06F12/1018

4. 发明授权

EP3534269B1 MEMORY INTERFACE 有权转让
公开(公告)号：EP3534269B1
公开(公告)日：2021-08-18
申请号：EP19159832.5
申请日：2019-02-27
发明人： ROBINSON, Martin John , LANDERS, Mark
IPC分类号： G06F12/0831 , G06F12/1018

5. 发明公开

EP3126984A4 CLUSTER-WIDE MEMORY MANAGEMENT USING SIMILARITY-PRESERVING SIGNATURES 审中-公开
公开(公告)号：EP3126984A4
公开(公告)日：2017-10-11
申请号：EP15773917
申请日：2015-03-25
申请人： STRATO SCALE LTD
发明人： HUDZIA BENOIT GUILLAUME CHARLES , FREIMAN ROM
IPC分类号： G06F12/00 , G06F3/06 , G06F9/455 , G06F9/50 , G06F12/08 , G06F12/0868 , G06F12/1018 , G06F15/16 , G06F17/30
CPC分类号： G06F3/0622 , G06F3/0631 , G06F3/0641 , G06F3/067 , G06F12/0868 , G06F12/1018 , G06F2212/657

6. 发明公开

EP3646188A1 METHODS OF MEMORY ADDRESS VERIFICATION AND MEMORY DEVICES EMPLOYING THE SAME 审中-公开
公开(公告)号：EP3646188A1
公开(公告)日：2020-05-06
申请号：EP18848662.5
申请日：2018-07-18
申请人： Micron Technology, Inc.
发明人： TROIA, Alberto
IPC分类号： G06F12/1018 , G06F12/02

7. 发明公开

EP3534269A1 MEMORY INTERFACE 有权转让
公开(公告)号：EP3534269A1
公开(公告)日：2019-09-04
申请号：EP19159832.5
申请日：2019-02-27
申请人： Imagination Technologies Limited
发明人： ROBINSON, Martin John , LANDERS, Mark
IPC分类号： G06F12/0831 , G06F12/1018
摘要： A memory interface for interfacing between a memory bus addressable using a physical address space and a cache memory addressable using a virtual address space, the memory interface comprising: a memory management unit configured to maintain a mapping from the virtual address space to the physical address space; and a coherency manager comprising a reverse translation module configured to maintain a mapping from the physical address space to the virtual address space; wherein the memory interface is configured to: receive a memory read request from the cache memory, the memory read request being addressed in the virtual address space; translate the memory read request, at the memory management unit, to a translated memory read request addressed in the physical address space for transmission on the memory bus; receive a snoop request from the memory bus, the snoop request being addressed in the physical address space; and translate the snoop request, at the coherency manager, to a translated snoop request addressed in the virtual address space for processing in connection with the cache memory.

8. 发明授权

EP2817741B1 METHOD AND APPARATUS UTILIZING NON-UNIFORM HASH FUNCTIONS FOR PLACING RECORDS IN NON-UNIFORM ACCESS MEMORY 有权
公开(公告)号：EP2817741B1
公开(公告)日：2018-12-26
申请号：EP13708027.1
申请日：2013-02-22
申请人： Hewlett Packard Enterprise Development LP
发明人： BEAVERSON, Arthur J. , BOWDEN, Paul , MANJANATHA, Sowmya , HUANG, Jinsong
IPC分类号： G06F3/06 , G06F17/30 , G06F12/02 , G06F12/0864 , G06F12/1018
CPC分类号： G06F3/0616 , G06F3/0611 , G06F3/064 , G06F3/0685 , G06F12/0246 , G06F12/0864 , G06F12/1018 , G06F17/30097 , G06F17/30949 , G06F2212/1036 , G06F2212/1044 , G06F2212/7201 , G06F2212/7202 , G06F2212/7208
摘要： Method and apparatus for storing records in non-uniform access memory. In various embodiments, the placement of records is localized in one or more regions of the memory. This can be accomplished utilizing different ordered lists of hash functions to preferentially map records to different regions of the memory to achieve one or more performance characteristics or to account for differences in the underlying memory technologies. For example, one ordered list of hash functions may localize the data for more rapid access. Another list of hash functions may localize the data that is expected to have a relatively short lifetime. Localizing such data may significantly improve the erasure performance and/or memory lifetime, e.g., by concentrating the obsolete data elements in one location. Thus, the two or more lists of ordered hash functions may improve one or more of access latency, memory lifetime, and/or operation rate.

9. 发明授权

EP3244324B1 SYSTEM FOR IMPLEMENTATION OF A HASH TABLE 有权
公开(公告)号：EP3244324B1
公开(公告)日：2018-09-12
申请号：EP17165860.2
申请日：2017-04-11
申请人： CESNET, zájmové sdruzení právnickych osob , Ceské vysoké ucení technické v Praze
发明人： BARTIK, Matej , UBIK, Sven
IPC分类号： G06F17/30 , G06T9/00 , H03M7/30 , H03M7/40 , H04L12/741 , G06F12/06 , G06F12/1018 , G11C7/10 , G11C8/12
CPC分类号： G11C7/1012 , G06F12/0623 , G06F12/1018 , G06F2212/401 , G11C7/1009 , G11C8/12 , H03M7/3086 , H03M7/40
摘要： The system contains at least one basic block (1). Each basic block (1) is formed by the first multiplexer (2), which has the first and second address inputs, and its output is connected to the address input (7) of the flag register memory (4), implemented as a LUT table, and of the circuit for write permit (3) to the flag register memory (4), which is equipped with the input (8) of the control signal of writing to the flag register memory (4), hereinafter referred to only as the memory. The output of the circuit for write permit (3) to the memory (4) is connected to the input (10) of the write signal to the memory (4), which is further equipped with the clock signal input (11) and the data input. To this data input is, via the inverter (12), connected the input (9) of the control signal for initialization of the memory (4), which is also interconnected with the control input of the first multiplexer (2) and with the control input of the circuit for write permit (3) to the memory (4). The data output (13) from the memory (4) of each basic block (1) is connected to one input of the masking block (20) relevant for the given basic block (1). The outputs (21) of these masking blocks (20) are connected to the inputs of the second multiplexer (22), while its output (23) is the output of the system of flags. The input (8) of the control signal for writing to the memory (4) of each basic block (1) is connected to the output of the demultiplexer (18) and simultaneously to the second input of the masking block (20) relevant for the given basic block (1). The demultiplexer (18) is equipped with the input (19) of the write permit signal, and the address input (17), which is interconnected with the output of the address splitter (15) equipped with the input (16) of the address for the whole system of flags for normal operating mode with the width of K bits, where K is a positive integer number, and with the output (5) of the address signal for addressing the memory (4) during normal operating mode, which is interconnected with the first address inputs of the first multiplexers (2) of all basic blocks (1). The second address inputs of the first multiplexers (2) of all basic blocks (1) are interconnected with the output (6) of the address signal for addressing the memory (4) for the counter (14) initialization mode, while one input of the counter (14) is interconnected with the inputs (9) of the control signal for the initialization of the memory (4) of the basic blocks (1) and the second input is the input of the clock signal.

10. 发明公开

EP3262532A4 DATA TYPE MANAGEMENT 审中-公开
公开(公告)号：EP3262532A4
公开(公告)日：2018-07-18
申请号：EP15910962
申请日：2015-12-18
申请人： HEWLETT PACKARD ENTPR DEVELOPMENT LP
发明人： GOLDSACK PATRICK , MONAHAN BRIAN QUENTIN , SALTER JAMES , BALDWIN ADRIAN JOHN
IPC分类号： G06F8/41 , G06F3/06 , G06F12/1018 , G06F17/30
CPC分类号： G06F12/1018 , G06F3/0619 , G06F3/0649 , G06F3/065 , G06F3/0679 , G06F8/437 , G06F2212/401
摘要： In one example in accordance with the present disclosure, a method for data type management may include adding a first data to a first data set. The first data set may belong to a plurality of data sets stored in a memory and each data set in the plurality may correspond to a type table defining data types in the corresponding data set. The method may further include determining that a first data type of the first data is not in a first type table corresponding to the first data set and generating an identifier corresponding to the first data type. The identifier may identify uses of the first data type within each data set in the plurality and may be a standardized value that is used by each data set in the plurality. The method may also include inserting the identifier into the first type table.

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