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1. 发明公开

EP2528232A4 INJECTION-LOCKED FREQUENCY DIVIDER AND PLL CIRCUIT 审中-公开
标题翻译：注射同步化分频器和PLL电路
公开(公告)号：EP2528232A4
公开(公告)日：2016-10-19
申请号：EP11734525
申请日：2011-01-21
申请人： PANASONIC IP MAN CO LTD
发明人： SHIMA TAKAHIRO , SATO JUNJI , KOBAYASHI MASASHI
IPC分类号： H03K3/354 , H03K3/03 , H03K3/2885 , H03K27/00 , H03L7/08 , H03L7/10
CPC分类号： H03K3/2885 , H03L7/08
摘要： An injection locked frequency divider and a PLL circuit, having a wide operating frequency bandwidth and capable of reducing the influence of any parasitic capacitance, are provided. Injection locked frequency divider (100) includes ring oscillator 140 that cascade-connects first amplifier circuit (141) including N-channel MOS transistor (111) and P-channel MOS transistor (112), and second amplifier circuit 142 and third amplifier circuit (143) that have the same configuration as first amplifier circuit (141) in three stages in a ring; N-channel MOS transistor 150 in which the sources of N-channel MOS transistors (111, 121, 131) in the respective stages are connected to the drain thereof; and differential signal injection circuit (160) that injects injection signal 11 to the gates of P-channel MOS transistors (112, 122, 132) in the respective stages and injects a reverse phase signal of injection signal 11 as a differential signal to the gate of N-channel MOS transistor (150).

2. 发明授权

EP2589146B1 ELEKTRONISCHE SCHALTUNG ZUR OPTISCHEN ANSTEUERUNG EINES FLIP FLOP 有权
标题翻译：电子电路对触发器的光学控制
公开(公告)号：EP2589146B1
公开(公告)日：2015-04-08
申请号：EP11721502.0
申请日：2011-05-18
申请人： Rohde & Schwarz GmbH & Co. KG
发明人： LANDOLT, Oliver
IPC分类号： H03K3/42 , H03K3/2885
CPC分类号： H03K17/78 , H03K3/2885 , H03K3/42

3. 发明授权

EP0688100B1 High speed comparator having two differential amplifier stages and latch stage 失效
标题翻译：具有两个差分放大器级和一个锁存级快速比较
公开(公告)号：EP0688100B1
公开(公告)日：2001-07-25
申请号：EP95109180.0
申请日：1995-06-14
申请人： NEC CORPORATION
发明人： Sone, Kazuya, c/o NEC Corporation
IPC分类号： H03K3/2885 , H03K3/012
CPC分类号： H03K3/012 , H03K3/2885

4. 发明公开

EP0379443A3 Logic circuit having flip-flop function 失效
标题翻译：具有FLIP-FLOP功能的逻辑电路
公开(公告)号：EP0379443A3
公开(公告)日：1991-09-11
申请号：EP90400158.3
申请日：1990-01-19
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Kitsuta, Tatsuaki , Shimotsuhama, Isao , Watanabe, Yoshio , Tanaka, Masahiro , Shiotsu, Shinichi , Ogawa, Kazumi
IPC分类号： H03K3/037 , H03K3/2885
CPC分类号： H03K3/2885
摘要： A logic circuit comprises a first terminal (D, D , 102a, 102b) for receiving an input data signal (D, D ), a second terminal (C, 106) for receiving a clock signal (C, CLK*), a first latch circuit (32, 121-123) coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit (33, 124, 125) coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal (Q, Q , 103a, 103b) for outputting an output data signal (Q, Q ) which is output from the second latch circuit, and a selecting part (30, 104, 121, 122) coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode.

5. 发明公开

EP0379443A2 Logic circuit having flip-flop function 失效
标题翻译： Logische Schaltung mit Flipflop-Funktion。
公开(公告)号：EP0379443A2
公开(公告)日：1990-07-25
申请号：EP90400158.3
申请日：1990-01-19
申请人： FUJITSU LIMITED , FUJITSU VLSI LIMITED
发明人： Kitsuta, Tatsuaki , Shimotsuhama, Isao , Watanabe, Yoshio , Tanaka, Masahiro , Shiotsu, Shinichi , Ogawa, Kazumi
IPC分类号： H03K3/037 , H03K3/2885
CPC分类号： H03K3/2885
摘要： A logic circuit comprises a first terminal (D, D , 102a, 102b) for receiving an input data signal (D, D ), a second terminal (C, 106) for receiving a clock signal (C, CLK*), a first latch circuit (32, 121-123) coupled to the first and second terminals for latching the input data signal responsive to the clock signal, a second latch circuit (33, 124, 125) coupled to the first latch circuit for latching an output signal of the first latch circuit, a third terminal (Q, Q , 103a, 103b) for outputting an output data signal (Q, Q ) which is output from the second latch circuit, and a selecting part (30, 104, 121, 122) coupled to the third terminal for selectively feeding back the output data signal to the first latch circuit in a first mode and for cutting off the feedback of the output data signal to the first latch circuit in a second mode, where the logic circuit operates as a toggle flip-flop in the first mode and operates as a delay flip-flop in the second mode.
摘要翻译：逻辑电路包括用于接收输入数据信号（D，D）的第一端（D，D，102a，102b），用于接收时钟信号（C，CLK *）的第二端（C，锁存电路（32,121-123），耦合到第一和第二端子，用于响应于时钟信号锁存输入数据信号;第二锁存电路（33,124,125），耦合到第一锁存电路，用于锁存输出信号，用于输出从第二锁存电路输出的输出数据信号（Q，Q）的第三端（Q，Q，103a，103b）和选择部分（30,104,121,122 ）耦合到第三端子，用于以第一模式选择性地将输出数据信号反馈到第一锁存电路，并以第二模式将输出数据信号的反馈切断到第一锁存电路，其中逻辑电路以在第一模式中的触发触发器，并且在第二模式中用作延迟触发器。

6. 发明公开

EP0371291A2 Mixed CML/ECL macro circuitry 失效
标题翻译： Kombinierte CML / ECL-Schaltung。
公开(公告)号：EP0371291A2
公开(公告)日：1990-06-06
申请号：EP89120717.7
申请日：1989-11-08
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Franz, Michael , Whang, Tsung Chuan
IPC分类号： H03K3/2885 , H03K19/086
CPC分类号： H03K3/2885
摘要： A circuit technique is presented for mixing current mode logic and emitter coupled logic in a manner which reduces active and passive component counts for performing recognized logic functions. The reduced counts permit greater circuit density while reducing power consumption in comparison to conventional emitter coupled logic circuitry. The mixing is also provided in a way for making all inputs and outputs compatible with conventional emitter coupled lologic levels. Various logic circuits are illustrated to demonstrate the versatility of the technique. For example, a transparent high D-latch (Fig. 2), a D flip-flop with true output (Fig. 4), a two-to-one multiplex latch (Fig. 6), and other D flip-flops having set and reset inputs (Fig. 7), multiplex data inputs (Fig. 8), and Exclusive OR data inputs (Fig. 9) are circuits wherein the inventive technique is employed to advantage.
摘要翻译：提出了一种电路技术，用于以减少用于执行识别的逻辑功能的有源和无源元件计数的方式混合电流模式逻辑和发射极耦合逻辑。与传统的发射极耦合逻辑电路相比，减少的计数允许更大的电路密度，同时降低功耗。还提供混合，使得所有输入和输出与常规发射器耦合的逻辑电平兼容。示出了各种逻辑电路以证明该技术的多功能性。例如，透明高D锁存器（图2），具有真实输出的D触发器（图4），二对一多路锁存器（图6）和其他D触发器，其具有设置和复位输入（图7），复用数据输入（图8）和异或数据输入（图9）是其中利用本发明技术的电路。

7. 发明公开

EP0206891A2 Emitter coupled logic latch with boolean logic input gating network. 失效
标题翻译： Verriegelungsschaltung in emittergekoppelter Logik e eem Eingangs-SchaltnetzwerkfürBoolesche Logik。
公开(公告)号：EP0206891A2
公开(公告)日：1986-12-30
申请号：EP86401214
申请日：1986-06-05
申请人： DIGITAL EQUIPMENT CORP
发明人： SMITH WILLIAM H , DOUCETTE RICHARD L
IPC分类号： H03K3/286 , H03K3/2885 , H03K19/086
CPC分类号： H03K19/0866 , H03K3/2885
摘要： A latch circuit including an input logic network that incorporates emitter-coupled logic switching arrangements connected in multiple levels to perform logical operations on the received input signals. The latch circuit is controlled by differential clock signals coupled to a differential switch circuit that is connected to the input logic network to form another switch level. An output buffer is connected to the input logic network to generate output signals of selected logic voltage levels. When the differential clock signals are in a pass condition, the input logic network is enabled to transmit an output signal to the output buffer. When the differential clock signals are in a latch, or hold, condition, the input logic network is disabled and a feedback network is enabled to maintain the signal to the output buffer in the conditions it was in when the differential clock signals changed conditions.
摘要翻译：一种锁存电路，包括输入逻辑网络，该输入逻辑网络包含以多个级别连接的发射极耦合逻辑开关装置，以对所接收的输入信号执行逻辑运算。锁存电路由耦合到差分开关电路的差分时钟信号控制，差分开关电路连接到输入逻辑网络以形成另一个开关电平。输出缓冲器连接到输入逻辑网络以产生所选逻辑电压电平的输出信号。当差分时钟信号处于通过状态时，输入逻辑网络使能将输出信号发送到输出缓冲器。当差分时钟信号处于锁存或保持状态时，禁止输入逻辑网络，并且在差分时钟信号变化的条件下使反馈网络能够使信号保持在输出缓冲器中。

8. 发明公开

EP1844548A2 DEVICE COMPRISING A LATCH 审中-公开
标题翻译：用弹簧锁装置
公开(公告)号：EP1844548A2
公开(公告)日：2007-10-17
申请号：EP06710725.0
申请日：2006-01-23
申请人： Koninklijke Philips Electronics N.V.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , TOMBEUR, Antoon, M., H.
IPC分类号： H03K3/2885
CPC分类号： H03K3/2885
摘要： Devices (101-105) comprising latches (1-3) with tracking circuits (4) for, in tracking modes, tracking data signals and with deciding circuits (5) for, in deciding modes, deciding about the data signal can use their available time more efficiently by, in the tracking modes, preparing the deciding circuits (5). Thereto, the deciding circuits (5) are not to be switched between disabled/enabled situations, but are to be kept enabled. The tracking circuits (4), in the tracking modes, supply signal values derived from the data signals to the deciding circuits (5), and the deciding circuits (5), in the deciding modes, amplify the signal values. The tracking circuits (4) comprise diodes (21,22) to allow reduced voltage swings in the data signals to be sufficient for proper performances of the latch (1-3). Such reduced voltage swings allow the latches (1-3) to perform at higher speeds. The parasitic capacitors present between the cathodes of the diodes (21,22) form capacitances for storing the signal values and allow the deciding circuits (5) to be prepared.

9. 发明公开

EP0635943A3 Ausgangsstufe für digitale Stromschalter 失效
标题翻译： Ausgangsstufe数字Stromschalter。
公开(公告)号：EP0635943A3
公开(公告)日：1995-10-18
申请号：EP94109988.9
申请日：1994-06-28
申请人： SIEMENS AKTIENGESELLSCHAFT
发明人： Delker, Klaus, Ing. grad.
IPC分类号： H03K19/013 , H03K19/086 , H03K3/2885
CPC分类号： G11C7/1051 , G11C11/413 , H03K3/2885 , H03K17/04166 , H03K17/666 , H03K19/0136
摘要： Eine Ausgangsstufe für digitale Stromschalter enthält von komplementären Signalen gesteuerte Emitterfolgertransistoren (3, 4), deren Emitter über eine Umschalteinrichtung (6) mit einer Stromquelle (5) verbunden sind. Die Umschalteinrichtung (6) schaltet den von der Stromquelle (5) eingeprägten Strom auf den Emitter desjenigen Emitterfolgertransistors (3 bzw. 4), der gerade den H-Pegel führt. Die Umschalteinrichtung (6) enthält vorzugsweise zwei mit der Stromquelle verbundene emittergekoppelte Schalttransistoren (14, 15), deren Basisanschlüsse jeweils über je einen Bipolartransistor (17 bzw. 16) in Emitterfolgerschaltung mit dem Emitter eines der Emitterfolgertransistoren (3 bzw. 4) verbunden sind.
摘要翻译：该级包含由互补信号控制的射极跟随器晶体管（3,4），其发射极通过切换装置（6）连接到电流源（5）。切换装置（6）将由电流源（5）施加的电流切换到当前承载H电平的发射极跟随器晶体管（3或者分别为4）的发射极。切换装置（6）优选地包含两个发射极耦合的开关晶体管（14,15），其连接到电流源，并且其基极端子在每种情况下都通过一个双极晶体管（17，和，分别为16），作为射极跟随器连接到射极跟随器晶体管（3和4中的一个的发射极）。

10. 发明授权

EP0448834B1 Integrierte Flip-Flop-Schaltung 失效
标题翻译：集成触发器电路。
公开(公告)号：EP0448834B1
公开(公告)日：1995-05-03
申请号：EP90125312.0
申请日：1990-12-22
申请人： TEMIC TELEFUNKEN microelectronic GmbH
发明人： Tränkle, Günther, Dipl.-Phys.
IPC分类号： H03K3/2885 , H03K3/289 , H03K3/02 , H03K17/04
CPC分类号： H03K3/2885 , H03K3/012 , H03K3/289

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