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1. 发明授权

EP2367330B1 High-speed signaling systems with adaptable pre-emphasis and equalization 有权转让
公开(公告)号：EP2367330B1
公开(公告)日：2017-08-09
申请号：EP11170420.1
申请日：2006-01-20
申请人： Rambus Inc.
发明人： Zerbe, Jared L. , Chen, Fred F. , Ho, Andrew , Farjad-Rad, Ramin , Poulton, John W. , Donnelly, Kevin S. , Lebowitz, Brian
IPC分类号： H04L25/03
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

2. 发明公开

EP2378729A3 High-speed signaling systems with adaptable pre-emphasis and equalization 有权转让
标题翻译：具有可调节的预加重和均衡高速信号系统
公开(公告)号：EP2378729A3
公开(公告)日：2011-11-02
申请号：EP11170386.4
申请日：2006-01-20
申请人： Rambus Inc.
发明人： Zerbe, Jared L. , Chen, Fred F. , Ho, Andrew , Farjad-Rad, Ramin , Poulton, John W. , Donnelly, Kevin S. , Lebowitz, Brian
IPC分类号： H04L25/03 , H04L7/033 , H04L1/00
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

3. 发明授权

EP1145511B1 EQUALIZER FOR MULTI-PAIR GIGABIT ETHERNET 有权
标题翻译：均衡器VIELPAARIGES千兆以太网
公开(公告)号：EP1145511B1
公开(公告)日：2010-08-04
申请号：EP99960364.0
申请日：1999-11-12
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar, E. , KRUSE, David , ABNOUS, Arthur , HATAMIAN, Mehdi
IPC分类号： H04L25/00
CPC分类号： G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0062 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/03885 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745

4. 发明公开

EP1362428A4 APPARATUS FOR AND METHOD OF REDUCING INTERFERENCE IN A COMMUNICATIONS RECEIVER 审中-公开
标题翻译：方法和设备在通信接收机的干扰减少
公开(公告)号：EP1362428A4
公开(公告)日：2009-12-02
申请号：EP02711194
申请日：2002-02-12
申请人： COMSYS COMM & SIGNAL PROC LTD
发明人： KLEINERMAN ALEXANDER , ZALTSMAN ARIEL , NAVON EDO , BACHAR YUVAL
IPC分类号： H04B1/10 , H04L25/03 , H03H7/40
CPC分类号： H04L25/03267 , H04B1/1027 , H04L25/03299 , H04L2025/03407 , H04L2025/03503

5. 发明公开

EP2043280A1 WAVEFORM EQUALIZING DEVICE 审中-公开
标题翻译： VORRICHTUNG ZUM ENTZERREN VON WELLENFORMEN
公开(公告)号：EP2043280A1
公开(公告)日：2009-04-01
申请号：EP07830191.8
申请日：2007-10-19
申请人： Panasonic Corporation
发明人： KIMURA, Yousuke c/o Panasonic Corporation , TAKANO, Haruka c/o Panasonic Corporation , AZAKAMI, Hiroshi c/o Panasonic Corporation
IPC分类号： H04B7/005 , H04B3/04
CPC分类号： H04B3/142 , H04L25/03038 , H04L25/03057 , H04L27/06 , H04L2025/03382 , H04L2025/03503 , H04L2025/03687 , H04L2025/037
摘要： Tap coefficients of an FIR filter are prevented from converging to wrong values. A waveform equalizer for performing waveform equalization of an input signal and outputting a waveform equalization result as an output signal includes: an FIR filter for performing a convolution operation between the input signal and a plurality of tap coefficients; an IIR filter for performing a convolution operation between the output signal and a plurality of tap coefficients; an adding section for adding an operation result of the FIR filter and an operation result of the IIR filter and outputting an addition result as the output signal; an error detecting section for detecting an error of the output signal; and a tap coefficient updating section for updating respective tap coefficients of the FIR filter and the IIR filter based on the error. The tap coefficient updating section sets a step size for updating the tap coefficients of the FIR filter to a value smaller than a step size for updating the tap coefficients of the IIR filter during a period from start of operation of the waveform equalizer until a predetermined condition is satisfied.
摘要翻译：阻止FIR滤波器的抽头系数收敛到错误的值。用于执行输入信号的波形均衡并输出波形均衡结果作为输出信号的波形均衡器包括：FIR滤波器，用于执行输入信号和多个抽头系数之间的卷积运算; IIR滤波器，用于在输出信号和多个抽头系数之间执行卷积运算; 添加部分，用于添加FIR滤波器的运算结果和IIR滤波器的运算结果，并输出相加结果作为输出信号; 用于检测输出信号的误差的检错部分; 以及抽头系数更新部分，用于基于该误差来更新FIR滤波器和IIR滤波器的各抽头系数。抽头系数更新部分将用于将FIR滤波器的抽头系数更新为小于用于在从波形均衡器的操作开始到预定条件的期间内更新IIR滤波器的抽头系数的步长的值的步长满意

6. 发明授权

EP1618597B1 Partial response receiver 有权转让
标题翻译：部分响应接收器
公开(公告)号：EP1618597B1
公开(公告)日：2009-03-25
申请号：EP04759335.5
申请日：2004-04-09
申请人： Rambus, Inc.
发明人： STOJANOVIC, Vladimir, M. , HOROWITZ, Mark, A. , ZERBE, Jared, L. , BESSIOS, Anthony , HO, Andrew, C., C. , WEI, Jason, C. , TSANG, Grace , GARLEPP, Bruno, W.
IPC分类号： H04L25/06
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： The present invention relates to a clock data recovery circuit (600) comprising a data sampling circuit (601) to generate data samples of an input data signal (D N ) response to a first clock signal (210); an edge sampling circuit (607) to generate edge samples of the input data signal in response to a second clock signal (610); and a clock recovery circuit (605) coupled to receive the edge samples and the data samples, the clock recovery circuit being configured to adjust a phase of the second clock signal according to the state of one of the edge samples upon determining that a sequence of at least three of the data samples matches at least one sample pattern of a plurality of predetermined sample patterns.
摘要翻译：接收电路，用于接收通过电信号导体传输的信号。第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。第一选择电路接收来自第一和第二采样电路的第一和第二采样值，并根据先前产生的采样值选择第一采样值或第二采样值作为选择的采样值输出。

7. 发明授权

EP1171982B1 GIGABIT ETHERNET WITH TIMING OFFSETS BETWEEN TWISTED-PAIR CONDUCTORS 有权
标题翻译：带移位的双绞线之间的时间千兆ETHERNT
公开(公告)号：EP1171982B1
公开(公告)日：2007-07-25
申请号：EP00926381.5
申请日：2000-04-24
申请人： Broadcom Corporation
发明人： CREIGH, John, L.
IPC分类号： H04L25/14
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs and the status signals, to the DSP and the PCS.

8. 发明公开

EP1547239A1 DIRECT CONVERSION RECEIVER AND RECEIVING METHOD 审中-公开
标题翻译：直接转换接收器和接收方法
公开(公告)号：EP1547239A1
公开(公告)日：2005-06-29
申请号：EP02758505.8
申请日：2002-09-16
申请人： Nokia Corporation
发明人： COERSMEIER, Edmund
IPC分类号： H03D3/00 , H04L27/38
CPC分类号： H04L25/03019 , H03D3/009 , H04L27/3863 , H04L27/3872 , H04L2025/0342 , H04L2025/03503 , H04L2027/0057
摘要： The invention relates to a receiving method and a direct conversion receiver. The receiver comprises a mixer (308) for mixing a received signal into a base band signal comprising I and Q branches, and an A/D converter (316) for converting the base band signal into digital form, and a phase adjuster (318) for performing a frequency selective IQ phase error estimation and for correcting the digitised signal with frequency selective correction factors based on the error estimation.
摘要翻译：本发明涉及接收方法和直接转换接收机。该接收机包括用于将接收信号混合成包括I和Q分支的基带信号的混频器（308）以及用于将基带信号转换成数字形式的A / D转换器（316），以及相位调整器（318）用于执行频率选择性IQ相位误差估计以及用于基于误差估计利用频率选择性校正因子校正数字化信号。

9. 发明公开

EP1384361A1 SYSTEM AND METHOD FOR TERRESTRIAL HIGH-DEFINITION TELEVISION RECEPTION 审中-公开
标题翻译：系统和方法用于地面高清晰度电视接收
公开(公告)号：EP1384361A1
公开(公告)日：2004-01-28
申请号：EP02715214.9
申请日：2002-03-28
申请人： Broadcom Corporation
发明人： PERLOW, Randall , BROOKS, Charles , JAFFE, Steven , LIU, Tianmin
IPC分类号： H04L27/06 , H04B1/10
CPC分类号： H04L25/0224 , H04L27/0008 , H04L2025/03503
摘要： An adaptive receiver is disclosed for optimally receiving and processing signals. The receiver utilizes one or more memory blocks (501) to store groups of incoming symbols. The groups of symbols are processed by a channel estimation subsystem (513) to determine channel characteristics. The receiver determines the appropriate demodulation and decoding strategy (529) to implement based on the determined channel characteristics. The receiver includes a plurality of demodulation and decoding schemes, one of which is selected based on the results of a channel estimation analysis.

10. 发明公开

EP1129553A2 MULTI-PAIR GIGABIT ETHERNET TRANSCEIVER 有权
标题翻译：作决定返回的方法和系统解码耦合
公开(公告)号：EP1129553A2
公开(公告)日：2001-09-05
申请号：EP99963877.8
申请日：1999-11-09
申请人： Broadcom Corporation
发明人： AGAZZI, Oscar, E. , CREIGH, John, L. , HATAMIAN, Mehdi , KRUSE, David, E. , ABNOUS, Arthur , SAMUELI, Henry
IPC分类号： H04L25/14 , H04L1/00 , H04L25/06 , H04L25/497 , H04L25/03 , H04L25/49 , H04L7/02 , H04L7/033 , H04B3/23 , H04B3/52
CPC分类号： H04L7/0062 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages: a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

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