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1. 发明公开

EP1239593A3 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：EP1239593A3
公开(公告)日：2004-01-21
申请号：EP01309751.4
申请日：2001-11-20
申请人： FUJITSU LIMITED
发明人： Yoshioka, Masato, c/o Fujitsu Limited , Tsukamoto, Sanroku, c/o Fujitsu Microelectronics
IPC分类号： H03M1/16 , H03M1/12
CPC分类号： H03M1/1215 , H03M1/069 , H03M1/1004 , H03M1/1023 , H03M1/146 , H03M1/205 , H03M1/365
摘要： An A/D converter comprises: a differential amplifier row (2) for amplifying differential voltages between an analog input voltage (VIN) and reference voltages (VRL, VR 1 ,..VR 5 , VRH); a first sample/hold circuit row (3) for sampling/holding the individual differential voltages amplified; a second sample/hold circuit row (4) having a pair of second and third sample/hold circuits connected in parallel to each output of the first sample/hold circuit row (3), thereby performing alternate sampling; a plurality of comparators (5) for determining whether the individual differential voltages held by the first sample/hold circuit row are positive or negative; and an encoder (6) for outputting digital code corresponding to the outputs of the comparators.

2. 发明授权

EP0319097B1 Complementary voltage interpolation circuit with transmission delay compensation 有权转让
标题翻译：互补Spannungsinterpolationsschaltung与传输延迟补偿。
公开(公告)号：EP0319097B1
公开(公告)日：1994-11-02
申请号：EP88202711.3
申请日：1988-11-28
申请人： Philips Electronics N.V.
发明人： Van de Plassche, Rudy Johan , Baltus, Peter Gerardus
IPC分类号： G06G7/30 , H03M1/44 , H03M1/00
CPC分类号： H03M1/205 , G06G7/30 , H03M1/141

3. 发明授权

EP1393447B1 CAPACITIVE FOLDING CIRCUIT FOR USE IN A FOLDING/INTERPOLATING ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译： CAPACITIVE折叠电路FOR USE IN A卷积内插模拟/数字变换器
公开(公告)号：EP1393447B1
公开(公告)日：2010-07-21
申请号：EP02720947.7
申请日：2002-02-11
申请人： Broadcom Corporation
发明人： BULT, Klaas
IPC分类号： H03M1/36
CPC分类号： H03M1/205 , H03M1/141

4. 发明公开

EP1239593A2 A/D converter 有权
标题翻译： A / D-Wandler
公开(公告)号：EP1239593A2
公开(公告)日：2002-09-11
申请号：EP01309751.4
申请日：2001-11-20
申请人： FUJITSU LIMITED
发明人： Yoshioka, Masato, c/o Fujitsu Limited , Tsukamoto, Sanroku, c/o Fujitsu Microelectronics
IPC分类号： H03M1/16
CPC分类号： H03M1/1215 , H03M1/069 , H03M1/1004 , H03M1/1023 , H03M1/146 , H03M1/205 , H03M1/365
摘要： An A/D converter comprises: a differential amplifier row (2) for amplifying differential voltages between an analog input voltage (VIN) and reference voltages (VRL, VR 1 ,..VR 5 , VRH); a first sample/hold circuit row (3) for sampling/holding the individual differential voltages amplified; a second sample/hold circuit row (4) having a pair of second and third sample/hold circuits connected in parallel to each output of the first sample/hold circuit row (3), thereby performing alternate sampling; a plurality of comparators (5) for determining whether the individual differential voltages held by the first sample/hold circuit row are positive or negative; and an encoder (6) for outputting digital code corresponding to the outputs of the comparators.
摘要翻译： A / D转换器包括：用于放大模拟输入电压（VIN）和参考电压（VRL，VR1，VR5，VRH）之间的差分电压的差分放大器行（2）。用于采样/保持放大的各个差分电压的第一采样/保持电路行（3）具有与第一采样/保持电路行（3）的每个输出并联连接的一对第二和第三采样/保持电路的第二采样/保持电路行（4），从而进行交替采样; 多个比较器（5），用于确定由第一采样/保持电路行保持的各个差分电压是正还是负; 以及用于输出与比较器的输出相对应的数字代码的编码器（6）。

5. 发明公开

EP0722633A1 FOLDING STAGE AND FOLDING ANALOG-TO-DIGITAL CONVERTER 失效
标题翻译：折叠舞台折叠模拟/数字转换器
公开(公告)号：EP0722633A1
公开(公告)日：1996-07-24
申请号：EP95921102.0
申请日：1995-06-27
申请人： Philips Electronics N.V.
发明人： NAUTA, Bram , VENES, Arnoldus, Gerardus, Wilhelmus
IPC分类号： H03M1
CPC分类号： H03M1/205 , H03M1/141
摘要： A folding stage (FB) for a folding analog-to-digital converter, the folding stage (FB) comprising: reference means having a plurality of consecutive reference terminals (RT1..RT11) for providing ascending different reference voltages; a first summing node (SNa), a second summing node (SNb) and a first output node (ONa); a plurality of differentially coupled transistor pairs (TAi/TBi), each one of the pairs comprising a first transistor (TAi) having a main current path and a control electrode which is coupled to an input terminal (IT) for receiving an input voltage to be folded and a second transistor (TBi) having a main current path and a control electrode which is coupled to a respective one (RTi) of the consecutive reference terminals, the main current path of the first transistor (TAi) of consecutive transistor pairs being coupled alternately to the first summing node (SNa) and the second summing node (SNb), and the main current path of the associated second transistor (TBi) being coupled alternately to the second summing node (SNb) and the first summing node (SNa); and current-to-voltage converter means (IVCONV) comprising a first resistor (12) connected between the first output node (ONa) and the first summing node (SNa) to provide a first output voltage (Va) and a transconductance stage (2) having an inverting input (4) coupled to the first summing node (SNa) and an output (8) coupled to the first output node (ONa). The low input impedance of the current-to-voltage converter means (IVCONV) prevents high voltage swing at the summing nodes and reduces capacitive signal current flow. The current-to-voltage converter means (IVCONV) further provides a high output voltage swing despite of loading with a low-ohmic interpolation network.

6. 发明公开

EP0319097A3 COMPLEMENTARY VOLTAGE INTERPOLATION CIRCUIT WITH TRANSMISSION DELAY COMPENSATION 有权转让
标题翻译：具有传输延迟补偿的补偿电压插补电路
公开(公告)号：EP0319097A3
公开(公告)日：1991-08-07
申请号：EP88202711
申请日：1988-11-28
申请人： N.V. PHILIPS' GLOEILAMPENFABRIEKEN
发明人： VAN DE PLASSCHE, RUDY JOHAN , BALTUS, PETER GERARDUS
IPC分类号： H03M1/12 , G06G7/30 , H03H17/00 , H03M1/14 , H03M1/20 , H03M1/36 , H03M1/44
CPC分类号： H03M1/205 , G06G7/30 , H03M1/141
摘要： The invention centers around a system for interpolating between multiple pairs of complementary main signals to generate further pair of complementary signals. An input circuit (10) supplies the main signals. The interpolation is a two-step operation. The first step is done with two strings (S and S
N ) of impedance elements (R₀ - R
N-1 and R
N0 - R
NN-1 ). Each pair of main signals is supplied to a corresponding pair of nodes along the strings. Interpolated signals are taken from other pairs of corresponding nodes along the strings. In the second interpolation stage, a delay network (D) formed with additional impedance elements (R
D0 - R
DN-1 and R
DN0 - R
DNN-1 ) compensates for transmission delays through the impedance elements that make up the strings.

7. 发明公开

EP2051382A4 FOLDING CIRCUIT AND ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译： UMLEGESCHALTUNG和模拟/数字转换器
公开(公告)号：EP2051382A4
公开(公告)日：2011-12-07
申请号：EP07806629
申请日：2007-09-04
申请人： SONY CORP
发明人： OHKAWA TAKESHI , ONO KOICHI , MATSUURA KOUJI , YAMASITA YUKITOSI , TOYOMURA JUNJI , NAKAMURA SHOGO , KANAGAWA NORIFUMI
IPC分类号： H03M1/36 , H03M1/06 , H03M1/08 , H03M1/14 , H03M1/20
CPC分类号： H03M1/0863 , H03M1/0682 , H03M1/141 , H03M1/205 , H03M1/365

8. 发明授权

EP1239593B1 A/D converter 有权
标题翻译： A / D转换器
公开(公告)号：EP1239593B1
公开(公告)日：2006-08-30
申请号：EP01309751.4
申请日：2001-11-20
申请人： FUJITSU LIMITED
发明人： Yoshioka, Masato, c/o Fujitsu Limited , Tsukamoto, Sanroku, c/o Fujitsu Microelectronics
IPC分类号： H03M1/16 , H03M1/12
CPC分类号： H03M1/1215 , H03M1/069 , H03M1/1004 , H03M1/1023 , H03M1/146 , H03M1/205 , H03M1/365

9. 发明授权

EP0840957B1 A/D CONVERTER WITH INTERPOLATION 失效
标题翻译：用内插法AD转换器
公开(公告)号：EP0840957B1
公开(公告)日：2002-03-27
申请号：EP96915124.0
申请日：1996-05-31
申请人： Koninklijke Philips Electronics N.V.
发明人： MORISSON, Richard , VORENKAMP, Pieter
IPC分类号： H03M1/44 , H03M1/20
CPC分类号： H03M1/205 , H03M1/365

10. 发明授权

EP0722632B1 FOLDING STAGE FOR A FOLDING ANALOG-TO-DIGITAL CONVERTER 失效转让
标题翻译：折叠舞台折叠模拟/数字转换器
公开(公告)号：EP0722632B1
公开(公告)日：2000-01-26
申请号：EP95921101.2
申请日：1995-06-27
申请人： Koninklijke Philips Electronics N.V.
发明人： VENES, Arnoldus, Gerardus, Wilhelmus , NAUTA, Bram
IPC分类号： H03M1/12
CPC分类号： H03M1/205 , H03M1/141

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