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1. 发明公开

EP3376531A1 SEMICONDUCTOR DEVICE COMPRISING A LATERALLY DIFFUSED TRANSISTOR 有权
公开(公告)号：EP3376531A1
公开(公告)日：2018-09-19
申请号：EP18159752.7
申请日：2014-02-28
申请人： LFoundry S.r.l.
发明人： Spitzlsperger, Gerhard , Schmidt, Carsten
IPC分类号： H01L21/768 , H01L21/74 , H01L21/762 , H01L29/66 , H01L29/417 , H01L29/78 , H01L21/8234
CPC分类号： H01L23/562 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823418 , H01L23/5226 , H01L23/528 , H01L24/43 , H01L27/092 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41708 , H01L29/4175 , H01L29/41766 , H01L29/66272 , H01L29/66333 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66712 , H01L29/732 , H01L29/7395 , H01L29/7398 , H01L29/74 , H01L29/7802 , H01L29/7811 , H01L29/7816 , H01L29/7823 , H01L29/7824 , H01L29/7835 , H01L29/808 , H01L2224/4502
摘要： A method of fabricating a semiconductor product includes the processing of a semiconductor wafer (10) from a front surface including structures disposed in the substrate (100) of the wafer adjacent to the front surface and the forming of at least one wiring (110) embedded in a dielectric layer (111) disposed on the front surface of the wafer. The semiconductor wafer is mounted to a carrier wafer (120) at its front surface so that material can be removed from the backside of the wafer to thin the semiconductor wafer. Backside processing of the semiconductor wafer includes the forming of implantations from the backside of the wafer, the forming of deep trenches (132a, 132b) to isolate the structures from other structures within the wafer, the forming of a through silicon via (134) to contact features on the frontside of the wafer and the forming of a body contact (131). Several devices, for example a LDMOS transistor with a body contact formed on the thinned backside, can be generated within the same wafer.

2. 发明公开

EP1835544A2 Semiconductor device and manufacturing method of the same 审中-公开
标题翻译： Halbleitervorrichtung und Herstellungsverfahrendafür
公开(公告)号：EP1835544A2
公开(公告)日：2007-09-19
申请号：EP07005474.7
申请日：2007-03-16
申请人： Sanyo Electric Co. Ltd. , Sanyo Semiconductor Co., Ltd.
发明人： Yanagida, Masamichi , Kameyama, Koujiro , Okada, Kikuo
IPC分类号： H01L29/78 , H01L29/739 , H01L29/417 , H01L29/06 , H01L29/08
CPC分类号： H01L29/7802 , H01L29/0653 , H01L29/0657 , H01L29/0696 , H01L29/0834 , H01L29/0886 , H01L29/41716 , H01L29/41741 , H01L29/41766 , H01L29/66734 , H01L29/7395 , H01L29/7397 , H01L29/7398 , H01L29/7809 , H01L29/7813 , H01L2924/10158
摘要： Thinning a semiconductor substrate (1) has been needed for reducing on-resistance in a semiconductor device such as a vertical MOS transistor, IGBT, or the like where a high current flows in the semiconductor substrate (1) in a vertical direction. In this case, the thinning is performed to the extent that the semiconductor substrate (1) does not warp with a heat treatment, so that there is a limitation in reduction of on-resistance. In the invention, openings (11) such as trench holes are formed on a back surface side of a semiconductor substrate (1). Then, a drain electrode (12) is formed being electrically connected with bottoms of these openings (11). In this case, a current path is formed short corresponding to the depths of the openings (11), thereby easily achieving low on-resistance.
摘要翻译：在半导体衬底（1）中沿垂直方向流过高电流的半导体器件（例如垂直MOS晶体管，IGBT等）中，需要使半导体衬底（1）变薄来降低导通电阻。在这种情况下，通过热处理使半导体基板（1）不翘曲的程度进行变薄，使得导通电阻的降低受到限制。在本发明中，在半导体基板（1）的背面侧形成有诸如沟槽的开口（11）。然后，形成与这些开口（11）的底部电连接的漏电极（12）。在这种情况下，对应于开口（11）的深度形成电流路径，从而容易实现低导通电阻。

3. 发明公开

EP1667237A2 Semiconductor switch device 有权
标题翻译： Halbleiterschaltungsanordnung
公开(公告)号：EP1667237A2
公开(公告)日：2006-06-07
申请号：EP05026273.2
申请日：2005-12-01
申请人： Nissan Motor Company, Ltd.
发明人： Shimoida, Yoshio , Hoshi, Masakatsu , Tanaka, Hideaki , Hayashi, Tetsuya , Shinohara, Toshiro , Yamagami, Shigeharu
IPC分类号： H01L29/78 , H01L29/739 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397
摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.
摘要翻译：本发明的一个方面提供了一种半导体器件，其包括：第一导电类型的第一半导体本体，设置在第一半导体本体上的第一开关机构，被配置和布置成用于接通流过半导体器件的导通/截止电流;以及设置在所述半导体主体上的第一反向阻挡异质结二极管，被配置和布置成阻止与所述第一开关机构的电流相反的电流接通/断开。

4. 发明公开

EP1367649A3 Power device having electrodes on a top surface thereof 审中-公开
标题翻译：与设置电极的表面上的功率器件
公开(公告)号：EP1367649A3
公开(公告)日：2006-04-12
申请号：EP03253092.5
申请日：2003-05-16
申请人： IXYS CORPORATION
发明人： Kelberlau, Ulrich , Zommer, Nathan
IPC分类号： H01L29/739 , H01L29/861 , H01L29/78 , H01L29/417 , H01L21/336 , H01L21/331
CPC分类号： H01L29/66712 , H01L29/0657 , H01L29/41766 , H01L29/66136 , H01L29/7398 , H01L29/7809 , H01L29/861 , H01L2224/16225 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/15311 , H01L2924/00
摘要： A power device includes a substrate assembly including an upper surface and a lower surface. The substrate assembly includes a first layer and a second layer. The first layer overlies the second layer and has different conductivity than the second layer. A first electrode is provided proximate the upper surface. A second electrode is provided proximate the upper surface and is spaced apart from the first electrode. The second layer is configured to provide a current path between the first and second electrodes.

5. 发明授权

EP0744769B1 Method of manufacturing MOS gate type power transistors 失效
标题翻译：一种用于制造MOS功率晶体管过程
公开(公告)号：EP0744769B1
公开(公告)日：2002-11-27
申请号：EP96107826.8
申请日：1996-05-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Han, Min-Koo , Yun, Chong-Man , Choi, Yearn-Ik
IPC分类号： H01L21/331
CPC分类号： H01L29/66325 , H01L29/1095 , H01L29/41766 , H01L29/6634 , H01L29/7396 , H01L29/7398 , H01L29/7802 , H01L29/7809
摘要： A method of forming a trench structure for a MOS gate type power transistor is disclosed. Beginning with a semiconductor structure which includes an epitaxial layer 3 having a trench 15 etched therein, a low concentration first diffusion region 35 is formed by thermal predeposition of a P-type conductive material into the trench 15. Next, a high concentration second diffusion region 17 is formed by ion implantation of the P-type conductive material into the first diffusion region 35 at the bottom of the trench 15. A third diffusion region 19 is formed by thermal predeposition of high concentration N-type conductive material on a sidewall of the trench 15. The second and third diffusion regions 17, 19 are simultaneously widened by thermal diffusion such that the second diffusion region 17 contacts and spans the bottom of the third diffusion region 19 during the thermal diffusion process. As both of the second and third diffusion regions 17, 19 are diffused simultaneously, the area under the third region 19 is always occupied by the heavily concentrated second region 17 regardless of diffusion time. The resulting structure reduces unnecessary body region resistance of the MOS transistor and produces a low forward voltage drop.

6. 发明公开

EP0837508A3 Semiconductor device and electric power conversion apparatus therewith 失效
标题翻译： Halbleiteranordnung und elektrische Leistungswandlungsvorrichtung
公开(公告)号：EP0837508A3
公开(公告)日：1999-01-20
申请号：EP97308267.0
申请日：1997-10-17
申请人： HITACHI, LTD.
发明人： Mori, Mutsuhiro , Uchino, Yoshihiro , Sakurai, Naoki , Kobayashi, Hideo , Sakano, Junichi
IPC分类号： H01L29/739
CPC分类号： H01L29/7398 , H01L29/0626 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/7393 , H01L29/7395 , H01L29/7397
摘要： In the IGBT having at least a p+n-pn+ structure from the collector to the emitter, the n layer with higher density than the n- layer is formed between the n- layer and the p layer. The n layer is a barrier for holes, and as the holes are stored in the n- layer, ON voltage is reduced.
摘要翻译：在从集电极到发射极的至少具有p + n-pn +结构的IGBT中，在n层和p层之间形成比n层高的n层。 n层是空穴的阻挡层，并且当孔存储在n层中时，导通电压降低。

7. 发明公开

EP0744769A3 MOS gate type power transistors 失效
标题翻译： MOS功率晶体管
公开(公告)号：EP0744769A3
公开(公告)日：1998-10-07
申请号：EP96107826
申请日：1996-05-16
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： HAN MIN-KOO , YUN CHONG-MAN , CHOI YEARN-IK
IPC分类号： H01L29/78 , H01L21/331 , H01L29/10 , H01L29/417 , H01L29/739
CPC分类号： H01L29/66325 , H01L29/1095 , H01L29/41766 , H01L29/6634 , H01L29/7396 , H01L29/7398 , H01L29/7802 , H01L29/7809
摘要： A method of forming a trench structure for a MOS gate type power transistor is disclosed. Beginning with a semiconductor structure which includes an epitaxial layer 3 having a trench 15 etched therein, a low concentration first diffusion region 35 is formed by thermal predeposition of a P-type conductive material into the trench 15. Next, a high concentration second diffusion region 17 is formed by ion implantation of the P-type conductive material into the first diffusion region 35 at the bottom of the trench 15. A third diffusion region 19 is formed by thermal predeposition of high concentration N-type conductive material on a sidewall of the trench 15. The second and third diffusion regions 17, 19 are simultaneously widened by thermal diffusion such that the second diffusion region 17 contacts and spans the bottom of the third diffusion region 19 during the thermal diffusion process. As both of the second and third diffusion regions 17, 19 are diffused simultaneously, the area under the third region 19 is always occupied by the heavily concentrated second region 17 regardless of diffusion time. The resulting structure reduces unnecessary body region resistance of the MOS transistor and produces a low forward voltage drop.

8. 发明公开

EP0760529A3 Lateral IGBT 失效
标题翻译：横向IGBT
公开(公告)号：EP0760529A3
公开(公告)日：1997-10-15
申请号：EP96306166.8
申请日：1996-08-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nakagawa, Akio, c/o K.K. Toshiba , Matsudai, Tomoko, c/o K.K. Toshiba , Funaki, Hideyuki, c/o K.K. Toshiba
IPC分类号： H01L29/739 , H01L29/10
CPC分类号： H01L29/66325 , H01L29/0696 , H01L29/7394 , H01L29/7398
摘要： A sub-gate electrode (20) is arranged to face, through a gate insulating film (19), a surface of a first p-type base layer (11) which is interposed between a first n-type source layer (13) and an n-type drift layer (4), and a surface of a second p-type base layer (14) which is interposed between a second n-type source layer (15) and the n-type drift layer (4) and faces the first p-type base layer (11). A main gate electrode (18) is arranged to face, through a gate insulating film (17), a surface of the second p-type base layer (14) which is interposed between the second n-type source layer (15) and the n-type drift layer (4) and does not face the first p-type base layer (11). Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer (11) and two n-type channels are to be formed in the second p-type base layer (14). The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 µm or less in the drifting direction.

9. 发明公开

EP0702411A3 High breakdown voltage semiconductor device with a buried MOS-gate structure 失效
标题翻译：具有高击穿电压和具有掩埋MOS栅结构的半导体器件
公开(公告)号：EP0702411A3
公开(公告)日：1997-06-04
申请号：EP95306441.7
申请日：1995-09-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Matsudai, Tomoko, c/o Int. Property Division , Kitagawa, Mitsuhiko, c/o Int. Property Division , Nakagawa, Akio, c/o Int. Property Division
IPC分类号： H01L29/739 , H01L29/78
CPC分类号： H01L29/0696 , H01L29/4238 , H01L29/7394 , H01L29/7398 , H01L29/7809 , H01L29/7824
摘要： A high breakdown voltage semiconductor device comprises a semiconductor substrate (1), an insulating film (2) formed on the semiconductor substrate (1), a first conductivity type active region (3) formed on the insulating film (2), a drain region (5) formed in a surface portion of the active region (3), second conductivity type base region (9) formed in a surface portion of the active region (3) at a distance from the drain region (5), a first conductivity type source region (8a, 8b, 8c) formed in a surface portion of the base region (9), a first gate insulating film (11a) formed on an inner surface of a first groove (10a) penetrating the base region (9) so as to come in contact with the source region (8a) and reaching the active region (3), a first gate electrode (12a) buried in the first groove (10a), on the inner surface of which the first gate insulating film (11a) is formed, a second gate insulating film (11b) formed on an inner surface of a second groove (10b) penetrating the base region (9) so as to come in contact with the source region (8b, 8c) in a position located apart from the first groove (10a) and reaching the active region (3), a second gate electrode (12b) buried in the second groove (10b), on the inner surface of which the second gate insulating film (11b) is formed, a source electrode (7) put in electrical contact with the source region (8a, 8b, 8c) and the base region (9), and a drain electrode (6) put in electrical contact with the drain region (5), characterized in that two or more channel regions are formed in a MOS structure constructed by the gate insulating film (11a, 11b), the gate electrode (12a, 12b), the source region (8a, 8b, 8c), the base region (9) and the active region (3).

10. 发明公开

EP0760529A2 Lateral IGBT 失效
标题翻译：横向IGBT
公开(公告)号：EP0760529A2
公开(公告)日：1997-03-05
申请号：EP96306166.8
申请日：1996-08-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nakagawa, Akio, c/o K.K. Toshiba , Matsudai, Tomoko, c/o K.K. Toshiba , Funaki, Hideyuki, c/o K.K. Toshiba
IPC分类号： H01L29/739 , H01L29/10
CPC分类号： H01L29/66325 , H01L29/0696 , H01L29/7394 , H01L29/7398
摘要： A sub-gate electrode (20) is arranged to face, through a gate insulating film (19), a surface of a first p-type base layer (11) which is interposed between a first n-type source layer (13) and an n-type drift layer (4), and a surface of a second p-type base layer (14) which is interposed between a second n-type source layer (15) and the n-type drift layer (4) and faces the first p-type base layer (11). A main gate electrode (18) is arranged to face, through a gate insulating film (17), a surface of the second p-type base layer (14) which is interposed between the second n-type source layer (15) and the n-type drift layer (4) and does not face the first p-type base layer (11). Three n-type MOSFETs are constructed such that one n-type channel is to be formed in the first p-type base layer (11) and two n-type channels are to be formed in the second p-type base layer (14). The three channels are to be formed, so that the channel width is effectively enlarged and the current density is increased. The second p-type base layer has a length of 10 µm or less in the drifting direction.
摘要翻译：子栅电极（20）通过栅极绝缘膜（19）设置在第一p型基极层（11）的表面，第一p型基极层（11）的介于第一n型源极层（13）和 n型漂移层（4）和介于第二n型源极层（15）和n型漂移层（4）之间的第二p型基极层（14）的表面，第一p型基底层（11）。主栅电极（18）通过栅极绝缘膜（17）设置在第二p型基极层（14）的介于第二n型源极层（15）和 n型漂移层（4），并且不面对第一p型基极层（11）。构造三个n型MOSFET，使得在第一p型基极层（11）中形成一个n型沟道，并且在第二p型基极层（14）中形成两个n型沟道，。要形成三个通道，从而有效地扩大通道宽度，增加电流密度。第二p型基层在漂移方向上的长度为10μm以下。

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