专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP1667237B1 Semiconductor switch device 有权
标题翻译：半导体电路
公开(公告)号：EP1667237B1
公开(公告)日：2012-02-22
申请号：EP05026273.2
申请日：2005-12-01
申请人： Nissan Motor Company, Ltd.
发明人： Shimoida, Yoshio , Hoshi, Masakatsu , Tanaka, Hideaki , Hayashi, Tetsuya , Shinohara, Toshiro , Yamagami, Shigeharu
IPC分类号： H01L29/78 , H01L29/739 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397

2. 发明公开

EP1667237A3 Semiconductor switch device 有权
标题翻译：半导体电路
公开(公告)号：EP1667237A3
公开(公告)日：2008-05-28
申请号：EP05026273.2
申请日：2005-12-01
申请人： Nissan Motor Company, Ltd.
发明人： Shimoida, Yoshio , Hoshi, Masakatsu , Tanaka, Hideaki , Hayashi, Tetsuya , Shinohara, Toshiro , Yamagami, Shigeharu
IPC分类号： H01L29/78 , H01L29/739 , H01L29/80 , H01L29/812
CPC分类号： H01L29/7398 , H01L29/0834 , H01L29/1608 , H01L29/267 , H01L29/7391 , H01L29/7392 , H01L29/7395 , H01L29/7397
摘要： An aspect of the present invention provides a semiconductor device that includes, a first semiconductor body of a first conductivity type, a first switching mechanism provided on the first semiconductor body, configured and arranged to switch on/off current flowing through the semiconductor device, and a first reverse-blocking heterojunction diode provided on the semiconductor body, configured and arranged to block current reverse to the current switched on/off by the first switching mechanism.

3. 发明公开

EP1469524A2 Insulated trench gate bipolar transistor 失效
标题翻译：双管晶体管分离器Graben-Gate
公开(公告)号：EP1469524A2
公开(公告)日：2004-10-20
申请号：EP04014331.5
申请日：1992-08-06
申请人： Kabushiki Kaisha Toshiba
发明人： Kitagawa, Mitsuhiko , Omura, Ichiro
IPC分类号： H01L29/739 , H01L29/423 , H01L29/745
CPC分类号： H01L29/7455 , H01L29/0696 , H01L29/4236 , H01L29/7394 , H01L29/7397 , H01L29/7398
摘要： A semiconductor device characterized by comprising:

a first semiconductor layer (12) of a second conductivity type, serving as a base layer;
a second semiconductor layer (16) of a first conductivity type disposed on the first semiconductor layer;
a plurality of trench like grooves (FIG.47) disposed in a surface of the first semiconductor layer at intervals, at a position remote from the second semiconductor layer, the plurality of trench like grooves comprising a first groove (20) interposed between a main region that serves as a current path and a dummy region covered with an insulating layer;
a third semiconductor layer (18) of the first conductivity type disposed on the first semiconductor layer on the main region side;
a fourth semiconductor layer (30) of the second conductivity type disposed on the third semiconductor layer;
a first main electrode (36) electrically connected to the second semiconductor layer;
a second main electrode (34) electrically connected to the fourth semiconductor layer;
a gate electrode (24) disposed in the first groove (20) to face, through a gate insulating film, a portion of the third semiconductor layer sandwiched between the first semiconductor layer and the fourth semiconductor layer, the gate electrode being configured to selectively induce a channel in the third semiconductor layer, which electrically connects the first semiconductor layer to the fourth semiconductor layer; and
a first additional semiconductor layer (114) of the first conductivity type disposed on the first semiconductor layer on the dummy region side, the first additional semiconductor layer having a bottom at a deeper position, as compared to that of the third semiconductor layer, in a depth direction of the first groove (20).
摘要翻译：一种半导体器件，其特征在于包括：第二导电类型的第一半导体层（12），用作基极层; 设置在第一半导体层上的第一导电类型的第二半导体层（16）在远离第二半导体层的位置处间隔设置在第一半导体层的表面中的多个沟槽状沟槽（图47），多个沟槽状沟槽包括插入主体之间的第一凹槽（20）作为电流路径的区域和覆盖有绝缘层的虚拟区域; 第一导电类型的第三半导体层（18）设置在主区域侧的第一半导体层上; 设置在第三半导体层上的第二导电类型的第四半导体层（30）电连接到第二半导体层的第一主电极（36）与第四半导体层电连接的第二主电极（34）设置在所述第一槽（20）中的栅电极（24），其通过栅极绝缘膜面对夹在所述第一半导体层和所述第四半导体层之间的所述第三半导体层的一部分，所述栅电极被配置为选择性地诱导第三半导体层中的沟道，其将第一半导体层与第四半导体层电连接; 以及设置在所述虚拟区域侧的所述第一半导体层上的所述第一导电类型的第一附加半导体层（114），所述第一附加半导体层具有与所述第三半导体层相比较深的位置的底部，第一凹槽（20）的深度方向。

4. 发明授权

EP0760529B1 Lateral IGBT 失效
标题翻译：横向IGBT
公开(公告)号：EP0760529B1
公开(公告)日：2002-12-18
申请号：EP96306166.8
申请日：1996-08-23
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nakagawa, Akio, c/o K.K. Toshiba , Matsudai, Tomoko, c/o K.K. Toshiba , Funaki, Hideyuki, c/o K.K. Toshiba
IPC分类号： H01L29/739 , H01L29/10 , H01L29/06
CPC分类号： H01L29/66325 , H01L29/0696 , H01L29/7394 , H01L29/7398

5. 发明公开

EP0837508A2 Semiconductor device and electric power conversion apparatus therewith 失效
标题翻译： Halbleiteranordnung und elektrische Leistungswandlungsvorrichtung
公开(公告)号：EP0837508A2
公开(公告)日：1998-04-22
申请号：EP97308267.0
申请日：1997-10-17
申请人： HITACHI, LTD.
发明人： Mori, Mutsuhiro , Uchino, Yoshihiro , Sakurai, Naoki , Kobayashi, Hideo , Sakano, Junichi
IPC分类号： H01L29/739
CPC分类号： H01L29/7398 , H01L29/0626 , H01L29/0847 , H01L29/1095 , H01L29/42368 , H01L29/7393 , H01L29/7395 , H01L29/7397
摘要： In the IGBT having at least a p+n-pn+ structure from the collector to the emitter, the n layer with higher density than the n- layer is formed between the n- layer and the p layer.
The n layer is a barrier for holes, and as the holes are stored in the n- layer, ON voltage is reduced.
摘要翻译：在从集电极到发射极的至少具有p + n-pn +结构的IGBT中，在n层和p层之间形成比n层高的n层。 n层是空穴的阻挡层，并且当孔存储在n层中时，导通电压降低。

6. 发明公开

EP0744769A2 MOS gate type power transistors 失效
标题翻译： MOS-Leistungstransistoren
公开(公告)号：EP0744769A2
公开(公告)日：1996-11-27
申请号：EP96107826.8
申请日：1996-05-16
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Han, Min-Koo , Yun, Chong-Man , Choi, Yearn-Ik
IPC分类号： H01L21/331 , H01L29/739
CPC分类号： H01L29/66325 , H01L29/1095 , H01L29/41766 , H01L29/6634 , H01L29/7396 , H01L29/7398 , H01L29/7802 , H01L29/7809
摘要： A method of forming a trench structure for a MOS gate type power transistor is disclosed. Beginning with a semiconductor structure which includes an epitaxial layer 3 having a trench 15 etched therein, a low concentration first diffusion region 35 is formed by thermal predeposition of a P-type conductive material into the trench 15. Next, a high concentration second diffusion region 17 is formed by ion implantation of the P-type conductive material into the first diffusion region 35 at the bottom of the trench 15. A third diffusion region 19 is formed by thermal predeposition of high concentration N-type conductive material on a sidewall of the trench 15. The second and third diffusion regions 17, 19 are simultaneously widened by thermal diffusion such that the second diffusion region 17 contacts and spans the bottom of the third diffusion region 19 during the thermal diffusion process. As both of the second and third diffusion regions 17, 19 are diffused simultaneously, the area under the third region 19 is always occupied by the heavily concentrated second region 17 regardless of diffusion time. The resulting structure reduces unnecessary body region resistance of the MOS transistor and produces a low forward voltage drop.
摘要翻译：公开了一种形成MOS栅型功率晶体管的沟槽结构的方法。从包括在其中蚀刻有沟槽15的外延层3的半导体结构开始，通过将P型导电材料热预沉积到沟槽15中，形成低浓度第一扩散区35.接下来，高浓度第二扩散区 17是通过在沟槽15的底部将P型导电材料离子注入到第一扩散区35中而形成的。第三扩散区19通过将高浓度N型导电材料热预沉积在沟槽15.第二和第三扩散区域17,19同时被热扩散加宽，使得第二扩散区域17在热扩散过程期间接触并跨越第三扩散区域19的底部。当第二和第三扩散区域17,19同时扩散时，第三区域19下面的区域总是被重度浓缩的第二区域17占据，而与扩散时间无关。所得到的结构减少了MOS晶体管的不必要的体区电阻并且产生低的正向压降。

7. 发明公开

EP0702411A2 High breakdown voltage semiconductor device with a buried MOS-gate structure 失效
标题翻译： Halbleiteranordnung mit hoher Durchbruchspannung und mit einer vergrabenen MOS-Gatestruktur
公开(公告)号：EP0702411A2
公开(公告)日：1996-03-20
申请号：EP95306441.7
申请日：1995-09-14
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Matsudai, Tomoko, c/o Int. Property Division , Kitagawa, Mitsuhiko, c/o Int. Property Division , Nakagawa, Akio, c/o Int. Property Division
IPC分类号： H01L29/739 , H01L29/78
CPC分类号： H01L29/0696 , H01L29/4238 , H01L29/7394 , H01L29/7398 , H01L29/7809 , H01L29/7824
摘要： A high breakdown voltage semiconductor device comprises a semiconductor substrate (1), an insulating film (2) formed on the semiconductor substrate (1), a first conductivity type active region (3) formed on the insulating film (2), a drain region (5) formed in a surface portion of the active region (3), second conductivity type base region (9) formed in a surface portion of the active region (3) at a distance from the drain region (5), a first conductivity type source region (8a, 8b, 8c) formed in a surface portion of the base region (9), a first gate insulating film (11a) formed on an inner surface of a first groove (10a) penetrating the base region (9) so as to come in contact with the source region (8a) and reaching the active region (3), a first gate electrode (12a) buried in the first groove (10a), on the inner surface of which the first gate insulating film (11a) is formed, a second gate insulating film (11b) formed on an inner surface of a second groove (10b) penetrating the base region (9) so as to come in contact with the source region (8b, 8c) in a position located apart from the first groove (10a) and reaching the active region (3), a second gate electrode (12b) buried in the second groove (10b), on the inner surface of which the second gate insulating film (11b) is formed, a source electrode (7) put in electrical contact with the source region (8a, 8b, 8c) and the base region (9), and a drain electrode (6) put in electrical contact with the drain region (5), characterized in that two or more channel regions are formed in a MOS structure constructed by the gate insulating film (11a, 11b), the gate electrode (12a, 12b), the source region (8a, 8b, 8c), the base region (9) and the active region (3).
摘要翻译：高耐压半导体器件包括半导体衬底（1），形成在半导体衬底（1）上的绝缘膜（2），形成在绝缘膜（2）上的第一导电类型有源区（3）（5）形成在有源区（3）的表面部分中的第二导电型基区（9），与有源区（3）的距离漏区（5）一定距离的表面部分中形成的第二导电型基区形成在基底区域（9）的表面部分中的第一栅极绝缘膜（11a，8a）形成在穿过基底区域（9）的第一凹槽（10a）的内表面上的第一栅极绝缘膜（11a）与源极区域（8a）接触并到达有源区域（3）;第一栅极电极（12a），其埋在第一沟槽（10a）中，第一栅极绝缘膜（ 11a），形成在穿过该基部的第二槽（10b）的内表面上的第二栅极绝缘膜（11b） e区域（9），以便在远离所述第一凹槽（10a）并且到达所述有源区域（3）的位置处与所述源极区域（8b，8c）接触;第二栅电极（12b）在其内表面上形成有第二栅极绝缘膜（11b）的第二沟槽（10b），与源极区域（8a，8b，8c）和基极区域（8a，8b，8c）电接触的源极（7） 9），以及与漏区（5）电接触的漏电极（6），其特征在于，在栅极绝缘膜（11a，11b）构成的MOS结构中形成有两个以上的沟道区，电极（12a，12b），源极区（8a，8b，8c），基极区（9）和有源区（3）。

8. 发明公开

EP0478004A3 Insulated gate transistor operable at a low drain-source voltage 失效
标题翻译：绝缘栅晶体管可在低漏源电压下工作
公开(公告)号：EP0478004A3
公开(公告)日：1992-05-06
申请号：EP91119868.7
申请日：1988-09-30
申请人： NEC CORPORATION
发明人： Ogawa, Kenji, c/o NEC Corporation
IPC分类号： H01L29/72 , H01L27/12 , H01L27/06 , H01L29/08
CPC分类号： H01L29/0834 , H01L29/41716 , H01L29/7395 , H01L29/7398 , H01L29/8605
摘要： A device comprising: A drain region (14,17) of a first conductivity type semiconductor having an upper surface portion and a bottom surface portion; a base region (41) of a second conductivity type semiconductor formed in said upper surface portion; a source region (40) of said first conductivity type semiconductor formed in said base region (41); a gate insulator film (48) formed on said second region positioned between said third and first regions; a gate electrode (49) formed on said gate insulator film (48); a source electrode (7-2) connected with said source region (40); an anode region (45) of said second conductivity type semiconductor formed in a first limited area of said drain region (14) apart from said base region (41); a resistive layer (18) formed in electrical contact with a second limited area of said drain region (17) apart from said base region (41) and said first limited area; and an anode electrode (7-1) contacting said anode region and said resistive layer (18), said resistive layer (18) presenting a predetermined value of resistance between said second limited area and said anode electrode (7-1), wherein said first limited area positions in said upper surface portion of said drain region.

9. 发明公开

EP0338312A3 Insulated gate bipolar transistor 失效
标题翻译：绝缘栅双极型晶体管
公开(公告)号：EP0338312A3
公开(公告)日：1990-03-21
申请号：EP89105833.1
申请日：1989-04-03
申请人： HITACHI, LTD.
发明人： Sakurai, Naoki , Mori, Mutsuhiro , Tanaka, Tomoyuki , Yasuda, Yasumichi , Nakano, Yasunori , Yatsuo, Tsutomu
IPC分类号： H01L29/72 , H01L29/08
CPC分类号： H01L29/0834 , H01L29/7398
摘要： An insulated gate bipolar transistor (IGBT) permits a large current to uniformly flow. A plurality of single crystal island regions (61) are formed in a supporting substrate (2) using dielectric films (1). Formed in each of the island regions are an n⁻ first region (61), a p second region (41) within the first region, an n⁺ third region (32) within the second region (41) and a p⁺⁺ fourth region (11) between the first region (61) and the dielectric film. All of these regions are exposed to the surface of the island region. Formed on the surface of the island region are a first main electrode (E) kept in ohmic contact with the second (41) and third (32) regions, a second main electrode (C) kept in ohmic contact with the fourth region (11) and a control electrode (G) located on the second (41) and third region (32) through an insulator (6).
摘要翻译：绝缘栅双极晶体管（IGBT）允许大电流均匀流动。使用介电膜（1）在支撑衬底（2）中形成多个单晶岛区（61）。形成在每个岛区中的是第一区域（61），第一区域内的第二区域（41），第二区域（41）内的第三区域（32）和第四区域（第四区域在第一区域（61）和电介质膜之间。所有这些地区都暴露在岛屿地区的表面。在岛区域的表面形成与第二区域（41）和第三区域（32）欧姆接触的第一主电极（E），与第四区域（11）保持欧姆接触的第二主电极）和通过绝缘体（6）位于第二区域（41）和第三区域（32）上的控制电极（G）。

10. 发明公开

EP0310112A3 Insulated gate transistor operable at a low drain-source voltage 失效
标题翻译：绝缘栅晶体管可在低漏源电压下工作
公开(公告)号：EP0310112A3
公开(公告)日：1989-05-24
申请号：EP88116192.1
申请日：1988-09-30
申请人： NEC CORPORATION
发明人： Ogawa, Kenji c/o NEC Corporation
IPC分类号： H01L29/72 , H01L27/06
CPC分类号： H01L29/0834 , H01L29/41716 , H01L29/7395 , H01L29/7398 , H01L29/8605
摘要： A transistor having a semiconductor substrate of a first conductivity type, a base region of a second conductivity type formed in the semiconductor substrate, a source region of the first conductivity type, a gate electrode formed on the base region between the source region and the semiconductor substrate via a gate insulator film, an additional region of the second conductivity type formed in the semiconductor substrate but separated from the base region, a resistive layer formed in electrically contact with an area of the semiconductor substrate which is separated from the base region and the additional region, a source electrode connected with the source region and a drain electrode connected with the additional region and the resistive layer.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式