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1. 发明公开

EP0655694A2 Discrete cosine transform processor 失效
标题翻译： Rechnerfürdie discrete Cosinus-Transformation。
公开(公告)号：EP0655694A2
公开(公告)日：1995-05-31
申请号：EP94118862.5
申请日：1994-11-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kim, Lee-Sup , Nagamatsu, Tetsu , Sakurai, Takayasu
IPC分类号： G06F17/14
CPC分类号： G06F17/147 , G06T9/007
摘要： Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image date to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.
摘要翻译：公开了一种改进的离散余弦变换处理器，包括用于接收要处理的图像日期的输入单元，用于预先存储关于图像输入数据和变换矩阵分量预先实现的乘法和累加计算的结果的存储单元，使得相同值从相同的读取行读取; 用于选择读取行的解码单元，其中由多个位组成的图像输入数据的每个位值用作一段地址数据; 用于累积从存储单元读取的数据的累加单元和用于输出积累处理结果作为输出数据的输出单元。存储单元在进行乘法运算和累计运算时，共同使用公用数据，因此能够减小存储容量，从而能够减小芯片面积。

2. 发明公开

EP0650128A3 Discrete cosine transform processor 失效
标题翻译：变换计算器离散余弦。
公开(公告)号：EP0650128A3
公开(公告)日：1995-06-07
申请号：EP94116934.4
申请日：1994-10-26
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Kim, Lee-Sup
IPC分类号： G06F17/14
CPC分类号： G06F17/147
摘要： A discrete cosine transform processor for executing discrete cosine transform calculations in both forward and inverse directions on the basis of previously stored product addition data has a memory having a first memory section (6a) for storing product addition calculation data for the forward direction transformation and a second memory section (6a) for storing product addition calculation data for the inverse direction transformation other than data in common to those stored in the first memory section; and sign inverter (7) for inverting signs of the data used in common for the inverse direction transformation, among the data stored in the first memory section. The memory preferably includes first memory for storing product addition data corresponding to even-order coefficients and second memory for storing product addition data corresponding to odd-order coefficients; and only the second memory stores data used in common for both the forward and inverse direction transformations in the first memory thereof.

3. 发明公开

EP0467361A1 BICMOS gate array device 失效
标题翻译： BICMOS门阵列-Anordnung。
公开(公告)号：EP0467361A1
公开(公告)日：1992-01-22
申请号：EP91112025.1
申请日：1991-07-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Momose, Hiroshi
IPC分类号： H01L27/118 , H01L27/07
CPC分类号： H01L27/11896
摘要： A semiconductor device has a plurality of basic cells fabricated on a single semiconductor substrate. Each of the basic cells comprises a first-conduction-type FETs (P3, P4; P5, P6), a second-conduction-type FETs (N3, N4; N5, N6), and a bipolar transistor (2, 4, 5). The collector region of the bipolar transistor is formed in a well region (2) where the first-conduction-type FETs are formed. The bipolar transistor is formed between the first-conduction-type FETs of adjacent ones of the basic cells separated by an element insulation film.
摘要翻译：半导体器件具有制造在单个半导体衬底上的多个基本单元。每个基本单元包括第一导电型FET（P3，P4; P5，P6），第二导电型FET（N3，N4; N5，N6）和双极晶体管（2,4,5 ）。双极晶体管的集电极区域形成在其中形成第一导电型FET的阱区（2）中。双极晶体管形成在由元件绝缘膜隔开的相邻的基本单元的第一导电型FET之间。

4. 发明公开

EP0329152A2 Semiconductor device with gate array 失效
标题翻译： Halbleiteranordnung mit Gattermatrix。
公开(公告)号：EP0329152A2
公开(公告)日：1989-08-23
申请号：EP89102755.9
申请日：1989-02-17
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hara, Hiroyuki , Sugimoto, Yasuhiro , Nagamatsu, Tetsu
IPC分类号： H01L27/06 , H03K19/082 , H03K19/094
CPC分类号： H03K19/09448 , H01L27/11896 , H03K19/1735
摘要： A semiconductor device is disclosed having a channeless gate array. A plurality of standard cells (11) are formed on a gate array chip such that one of the standard cells is formed relative to the adjacent standard cell with a bipolar transistor (21) and resistor (26) shared, as a BiCMOS logic gate, by the mutually adjacent standard cells at one end.
摘要翻译：公开了一种具有无通道门阵列的半导体器件。多个标准单元（11）形成在栅极阵列芯片上，使得标准单元之一相对于相邻的标准单元以双极晶体管（21）和电阻（26）形成，作为BiCMOS逻辑门，通过相邻的标准单元在一端。

5. 发明授权

EP0667681B1 Parallel-to-serial conversion device and linear transformation device making use thereof 失效
标题翻译：平行于使用该转换器的线性变换串行转换器和设备
公开(公告)号：EP0667681B1
公开(公告)日：2002-05-02
申请号：EP95101784.7
申请日：1995-02-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Matsui, Masataka
IPC分类号： H03M9/00 , G11C8/00 , G11C11/412 , G11C11/419
CPC分类号： G11C8/12 , H03M9/00

6. 发明授权

EP0467361B1 BICMOS gate array device 失效
标题翻译：的BiCMOS门阵列排列
公开(公告)号：EP0467361B1
公开(公告)日：1997-09-17
申请号：EP91112025.1
申请日：1991-07-18
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Momose, Hiroshi
IPC分类号： H01L27/118 , H01L27/07
CPC分类号： H01L27/11896

7. 发明公开

EP0788059A1 Driver circuit device 失效
标题翻译： Treiberschaltungsvorrichtung
公开(公告)号：EP0788059A1
公开(公告)日：1997-08-06
申请号：EP97101502.9
申请日：1997-01-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Kuroda, Tadahiro
IPC分类号： G06F13/40
CPC分类号： H04L25/0292 , G06F13/4072 , H04L25/0272 , H04L25/028 , Y02D10/14 , Y02D10/151
摘要： In the constant current drive type driver used for an LVDS (low voltage differential signal) interface, the parasitic capacitance of the package pins is charged and discharged sufficiently at a high speed to secure the high speed signal transmission operation. Further, the AC differential amplitude large enough to be received by the receiver can be obtained. The driver circuit device comprises: a transmit circuit composed of transistors (52, 53, 56, 57) for transmitting a signal by switching the signal current direction flowing through a pair of transmission lines (8, 9) connected between two output terminals (13 and 13B); and a constant current source composed of transistors (54, 75) for controlling the current value of the transmit circuit. In the idle state, only one of the two transistors (54 and 75) of the constant current source is turned on to limit the signal current flowing through the output terminals (13 and 13B). On the other hand, in the high speed signal transmission, both the transistors (54, 75) are turned on to increase the signal current flowing through the output terminals (13, 13B) to obtain a signal current of high DC LVDS level.
摘要翻译：在用于LVDS（低电压差分信号）接口的恒流驱动型驱动器中，封装引脚的寄生电容以高速充分充放电以确保高速信号传输操作。此外，可以获得足够大以由接收器接收的AC差分幅度。驱动器电路装置包括：由晶体管（52,53,56,57）组成的发送电路，用于通过切换流过连接在两个输出端子（13）之间的一对传输线（8,9）的信号电流方向来发送信号和13B）; 以及由用于控制发射电路的电流值的晶体管（54,75）组成的恒流源。在空闲状态下，恒流源的两个晶体管（54和75）中只有一个导通，以限制流过输出端子（13和13B）的信号电流。另一方面，在高速信号传输中，两个晶体管（54,75）导通，以增加流过输出端子（13,13b）的信号电流，以获得高DC LVDS电平的信号电流。

8. 发明授权

EP0788059B1 Driver circuit device 失效
标题翻译：驱动电路装置
公开(公告)号：EP0788059B1
公开(公告)日：2003-01-08
申请号：EP97101502.9
申请日：1997-01-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Kuroda, Tadahiro
IPC分类号： G06F13/40
CPC分类号： H04L25/0292 , G06F13/4072 , H04L25/0272 , H04L25/028 , Y02D10/14 , Y02D10/151
摘要： In the constant current drive type driver used for an LVDS (low voltage differential signal) interface, the parasitic capacitance of the package pins is charged and discharged sufficiently at a high speed to secure the high speed signal transmission operation. Further, the AC differential amplitude large enough to be received by the receiver can be obtained. The driver circuit device comprises: a transmit circuit composed of transistors (52, 53, 56, 57) for transmitting a signal by switching the signal current direction flowing through a pair of transmission lines (8, 9) connected between two output terminals (13 and 13B); and a constant current source composed of transistors (54, 75) for controlling the current value of the transmit circuit. In the idle state, only one of the two transistors (54 and 75) of the constant current source is turned on to limit the signal current flowing through the output terminals (13 and 13B). On the other hand, in the high speed signal transmission, both the transistors (54, 75) are turned on to increase the signal current flowing through the output terminals (13, 13B) to obtain a signal current of high DC LVDS level.

9. 发明公开

EP0655694A3 Discrete cosine transform processor 失效
标题翻译：变换计算器离散余弦。
公开(公告)号：EP0655694A3
公开(公告)日：1995-11-02
申请号：EP94118862.5
申请日：1994-11-30
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kim, Lee-Sup , Nagamatsu, Tetsu , Sakurai, Takayasu
IPC分类号： G06F17/14
CPC分类号： G06F17/147 , G06T9/007
摘要： Disclosed is an improved discrete cosine transform processor comprising an input unit for receiving image date to be processed, a storage unit for previously storing a result of a multiplication and accumulation calculation effected beforehand with respect to image input data and transform matrix components so that the same value is read from the same read line; a decoding unit for selecting the read line, in which each bit value of the image input data composed of a plurality of bits serves as a piece of address data; an accumulation unit for accumulating the data read from the storage unit and an output unit for outputting a result of the accumulation processing as output data. The storage unit uses the common data in common when effecting the multiplication and accumulation calculation, and, hence, a storage capacity is reduced, thereby making it possible to decrease a chip area.

10. 发明公开

EP0667681A2 Parallel-to-serial conversion device and linear transformation device making use thereof 失效
标题翻译：并串联变换装置和设备，用于线性变换模型与该转换装置的应用。
公开(公告)号：EP0667681A2
公开(公告)日：1995-08-16
申请号：EP95101784.7
申请日：1995-02-09
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Nagamatsu, Tetsu , Matsui, Masataka
IPC分类号： H03M9/00
CPC分类号： G11C8/12 , H03M9/00
摘要： A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in row direction of the input section and by reading out in the column direction of the input section, write section for selectively writing data into a first pair of memory cells of said corner turn memory array; and readout section for simultaneously reading data from a second pair of memory cells which are different from the first pair of memory cells.
摘要翻译：能够提高空间效率的并行至串行转换装置具有在该装置的输入部分设置在由所述输入部的行方向上写入以及执行并行 - 串行转换的拐角转弯存储器阵列通过在读出输入部的列方向上，写入部分，用于选择性地将数据写入到一个第一对所述拐角转弯存储器阵列的存储单元; 并同时从第二对存储器单元哪个是从所述第一对存储器单元的不同的读取数据读出部。

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