专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP2759926A1 Adder capable of supporting addition and subtraction 审中-公开
标题翻译： Addierer mitUnterstützungvon Addition und Subtraktion
公开(公告)号：EP2759926A1
公开(公告)日：2014-07-30
申请号：EP14152909.9
申请日：2014-01-28
申请人： Samsung Electronics Co., Ltd
发明人： Yu, Hyeong-Seok , Kim, Suk-Jin
IPC分类号： G06F7/507
CPC分类号： G06F17/10 , G06F7/503 , G06F7/507 , G06F2207/382 , G06F2207/3828
摘要： An adder for supporting multiple data types by controlling a carry propagation is provided. In an example, the adder supports a subtraction operation of a maximum n-bit data types, and includes a plurality of the first addition areas each formed with a predetermined unit number of bits and configured to receive pieces of incoming operand data, and one or more second addition areas each formed between the plurality of the first addition areas and configured to receive pieces of control data based on an operand data type and an operation type.
摘要翻译：提供了一种通过控制进位传播来支持多种数据类型的加法器。在一个示例中，加法器支持最大n位数据类型的减法运算，并且包括多个第一相加区域，每个第一加法区域以预定的单位数形式形成，并且被配置为接收输入的操作数数据，以及一个或多个第二相加区域分别形成在多个第一相加区域之间，并被配置为基于操作数数据类型和操作类型接收多条控制数据。

2. 发明公开

EP1662374A3 M-Bit carry select adder 审中-公开
标题翻译： M位进位选择加法器
公开(公告)号：EP1662374A3
公开(公告)日：2006-08-02
申请号：EP06003317.2
申请日：2001-09-19
申请人： STMicroelectronics, Inc.
发明人： Ballachino, William Elliott
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/50 , G06F2207/3876
摘要： An M-bit adder (300) capable of receiving a first M-bit argument (A0-A31), a second M-bit argument (B0-B31), and a carry-in (CI) bit comprising M adder cells (C0-C31) arranged in R rows, wherein each row generates a carry-out bit that is the carry-in bit to the next higher row, wherein a least significant adder cell (C0) in a first one of said rows of adder cells receives a first data bit, A x , from said first M-bit argument and a first data bit, B x , from said second M-bit argument, and generates a first conditional carry-out bit, C x (1), and a second conditional carry-out bit, C x (0), wherein said C x (1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding said first row is a 1 and said C x (0) bit is calculated assuming said row carry-out bit from said second row is a 0, characterised in that the least significant adder cell (C0) generates a first conditional sum bit S x (1) calculated assuming said row carry-out bit from said second row is a 1, and a second conditional sum bit S x (0) assuming said row carry-out bit from said second row is a 0, and wherein each row of adder cells contains N adder cells and said preceding row of adder cells contains less than N adder cells and physically locating the least significant adder cell of each of the 2nd to the R'th rows at the end of the preceding row.
摘要翻译：能够接收包括M个加法器单元（C0）的第一M位自变量（A0-A31），第二M位自变量（B0-B31）和进位（C1）位的M位加法器（300）其中每行产生一个进位比特，它是进位比特到下一个更高的行，其中所述加法器单元的第一行中的最低有效加法器单元（C0）接收来自所述第一M位自变量的第一数据位Ax和来自所述第二M位自变量的第一数据位Bx，并且生成第一条件执行位Cx（1）和第二条件进位（0），其中假定来自所述第一行之前的第二行加法器单元的行输出位是1并且所述Cx（0）位是假定所述Cx 其特征在于最低有效加法器单元（C0）产生假设来自所述第二行的所述行输出位为1而计算的第一条件和位Sx（1）和一秒钟假定来自所述第二行的所述行输出位为0，并且其中每行加法器单元包含N个加法器单元，并且所述前一行加法器单元包含少于N个加法器单元并物理定位在前一行结尾的第二行到第R行中每一行的最低有效加法单元。

3. 发明授权

EP0849663B1 Conditional sum adder using pass-transistor logic 失效
标题翻译：通过使用通晶体管逻辑加法器条件的总和
公开(公告)号：EP0849663B1
公开(公告)日：2003-11-19
申请号：EP97310722.0
申请日：1997-12-18
申请人： Samsung Electronics Co., Ltd.
发明人： Song, Min-Kyu
IPC分类号： G06F7/50 , G06F7/52
CPC分类号： G06F7/5318 , G06F7/507 , G06F2207/4816

4. 发明公开

EP1008033A1 DIGITAL ADDER CIRCUIT 失效
标题翻译：数字加法器
公开(公告)号：EP1008033A1
公开(公告)日：2000-06-14
申请号：EP97930628.9
申请日：1997-07-04
申请人： ARM Limited
发明人： LIU, Jianwei
IPC分类号： G06F7/50
CPC分类号： G06F7/506 , G06F7/507 , G06F2207/3876
摘要： A binary adder circuit includes carry evaluation circuits that encode a carry production control signal using two signal values (V, W) such that V = W = 0 indicates a carry kill, V = W = 1 indicates a carry generate and V =/ W indicates a carry propagate. The carry evaluation circuit may be implemented in static or dynamic CMOS logic.

5. 发明授权

EP0508627B1 Method and apparatus for generating carry out signals 失效
标题翻译：方法和装置，用于产生进位信号
公开(公告)号：EP0508627B1
公开(公告)日：1999-01-13
申请号：EP92302413.7
申请日：1992-03-20
申请人： SUN MICROSYSTEMS, INC.
发明人： Patel, Samir
IPC分类号： G06F7/50
CPC分类号： G06F7/507

6. 发明授权

EP0334768B1 Logic circuit having carry select adders 失效
标题翻译：加法器逻辑电路Uebertragungsgesteuerten
公开(公告)号：EP0334768B1
公开(公告)日：1997-10-08
申请号：EP89400856.4
申请日：1989-03-24
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke , Kubosawa, Hajime
IPC分类号： G06F7/50
CPC分类号： G06F7/507

7. 发明公开

EP0769738A2 Logic circuit and method for designing the same 失效
标题翻译：逻辑电路及其设计方法
公开(公告)号：EP0769738A2
公开(公告)日：1997-04-23
申请号：EP96116589.1
申请日：1996-10-16
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Kondo, Yoshihisa
IPC分类号： G06F7/48 , G06F7/50 , G06F7/52
CPC分类号： G06F7/535 , G06F7/48 , G06F7/5052 , G06F7/507 , G06F9/3867 , G06F17/5045 , G06F2207/3884 , G06F2207/5353
摘要： A logic circuit with a pipelined structure has a plurality stage of combinational circuits and memory circuits such as flip-flops connected among the pipeline combinational circuits. The pipeline combinational circuits constituting a logic circuit is operated at a cycle time shorter than a signal propagation time for the critical path of the pipeline combinational circuit. For the case of activation of the path not covered by this cycle time, another combinational circuit and its peripheral circuits are additionally provided for generating a correction signal. Another combinational circuit has substantially the same logic. The cycle time is determined so as to cover the critical path including another combinational circuit. A comparator circuit compares an output signal of another combinational circuit and an output signal of the combinational circuit. If both the signals are not coincident, a selector is controlled to correct the signal by using the output signal of another combinational circuit.
摘要翻译：具有流水线结构的逻辑电路具有多级组合电路和存储器电路，例如连接在流水线组合电路之间的触发器。构成逻辑电路的流水线组合电路在比流水线组合电路的关键路径的信号传播时间短的周期时间内工作。对于未被该周期时间覆盖的路径激活的情况，另外提供另一个组合电路及其外围电路用于产生校正信号。另一个组合电路具有基本相同的逻辑。周期时间被确定为覆盖包括另一个组合电路的关键路径。比较器电路比较另一个组合电路的输出信号和组合电路的输出信号。如果两个信号不一致，则控制选择器以通过使用另一个组合电路的输出信号来校正该信号。

8. 发明公开

EP0508627A3 Method and apparatus for generating carry out signals 失效
标题翻译：用于生成信号的方法和装置
公开(公告)号：EP0508627A3
公开(公告)日：1994-07-13
申请号：EP92302413.7
申请日：1992-03-20
申请人： SUN MICROSYSTEMS, INC.
发明人： Patel, Samir
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： A circuit for determining the carry out from the addition of two numbers independent of the determination of the sum of the two numbers including apparatus for determining a first carry out from each bit position for a carry in of a first value, apparatus for determining a second carry out from each bit position for a carry in of a second value, a plurality of apparatus for utilizing the first and second carry out values from two or more adjacent bit positions to produce a first carry out from each plurality of bit positions for a carry in of a first value, and second carry out from each plurality of bit positions for a carry in of a second value, and apparatus for selecting between the first and second values based on the actual values of the carry ins.
摘要翻译：一种电路，用于从独立于两个数字的和的确定确定进位，包括用于确定第一值的进位的每个比特位置的第一进位的装置，用于确定第二值的装置从每个比特位置执行用于第二值的进位，多个装置，用于利用来自两个或更多个相邻比特位置的第一和第二进位值从多个比特位置产生用于进位的第一进位并且从用于第二值的进位的每个多个位位置进行第二次执行，以及用于基于进位输入的实际值在第一和第二值之间进行选择的装置。

9. 发明公开

EP0520298A3 Arithmetic circuit 失效
标题翻译：算术电路
公开(公告)号：EP0520298A3
公开(公告)日：1993-07-14
申请号：EP92110155.6
申请日：1992-06-16
申请人： NEC CORPORATION
发明人： Suzuki, Kazumasa, c/o NEC Corporation
IPC分类号： G06F7/50 , G06F7/544
CPC分类号： G06F7/507 , G06F7/544 , G06F2207/5442
摘要： A carry propagation circuit (3) generating a block carry propagation function P as a signal at an intermediate junction of a carry lookahead circuit, on the basis of input two numbers A and B, and a carry generation circuit (4) for generating a block carry generation function G on the basis of the two numbers A and B, are provided. When a carry input is 0, a carry c₀ is the same value to the block carry generation function G. On the other hand, when the carry input is 1, the carry c₁ is an OR of the block carry generation function G and the block carry propagation function P, which can be obtained by an OR circuit (5). Two sums S₀ and S₁ are derived from two carries and an exclusive OR of two numbers A and B by exclusive OR circuits (6,7).
The circuit can be used in a carry-select adder or in an absolute difference calculating circuit.

10. 发明公开

EP0394610A3 Plural dummy select chain logic synthesis network 失效
标题翻译：多余的选择链逻辑综合网络
公开(公告)号：EP0394610A3
公开(公告)日：1992-07-15
申请号：EP90100775.7
申请日：1990-01-16
申请人： International Business Machines Corporation
发明人： Bechade, Robert Albert
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： A logic synthesis network for efficiently combining respective bit pairs of first and second operands to produce respective sum bits and a carry bit associated with the most significant sum bit. A dummy generator receives the respective bit pairs and generates first and second dummy sum signals, and first and second pairs of dummy carry signals. A first dummy selector chain selects the appropriate dummy sum and carry signals of all the bits other than the least significant bit, as a function of the state of the first pair of dummy carry signals generated for the least significant bit pair. A second dummy select chain selects the appropriate dummy sum and carry signals for all the bit pairs other than the least signficant bit pair, as a function of the state of the second pair of dummy carry signals generated for the least significant bit pair. Sum generators associated with each bit pair choose between the selected dummy sum signals from the first and second dummy select chains in accordance with the state of the carry-in signal associated with the least significant bit pair. Carry generators associated with each bit pair choose between the first and second pairs of dummy carry signals at the ends of the first and second dummy select chains, again in accordance with the state of the carry-in signal associated with the least significant bit pair.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式