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1. 发明授权

EP0347029B1 Binary carry or borrow look-ahead circuit 失效
标题翻译：二进制先行进位电路
公开(公告)号：EP0347029B1
公开(公告)日：1996-11-27
申请号：EP89303850.5
申请日：1989-04-19
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke , Kubosawa, Hajime
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/4812

2. 发明公开

EP0278463A3 Gate array having transistor buried in interconnection region 失效
标题翻译：在互连区域内具有晶体管的栅格阵列
公开(公告)号：EP0278463A3
公开(公告)日：1990-05-23
申请号：EP88101818.8
申请日：1988-02-08
申请人： FUJITSU LIMITED
发明人： Kubosawa, Hajime , Naitoh,Mitsugo
IPC分类号： H01L27/02 , H01L23/52
CPC分类号： H01L27/11807 , H01L23/535 , H01L2924/0002 , Y10S257/923 , H01L2924/00
摘要： A gate array comprises a semiconductor substrate (40), a plurality of mutually parallel basic cell columns (41) each made up of a plurality of basic cells (44, 44X, 44Y) formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions (42, 42S) each formed between two mutually adjacent ones of the basic cell columns and specific cells (47, 47X, 60, 60X) buried in one or a plurality of predetermined ones (42S) of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor (P3) and a second n-channel transistor (N3) which constitute a transmission gate.

3. 发明授权

EP0334768B1 Logic circuit having carry select adders 失效
标题翻译：加法器逻辑电路Uebertragungsgesteuerten
公开(公告)号：EP0334768B1
公开(公告)日：1997-10-08
申请号：EP89400856.4
申请日：1989-03-24
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke , Kubosawa, Hajime
IPC分类号： G06F7/50
CPC分类号： G06F7/507

4. 发明公开

EP0347029A2 Binary carry or borrow look-ahead circuit 失效
标题翻译： BinäreÜbertragvorgriffsschaltung。
公开(公告)号：EP0347029A2
公开(公告)日：1989-12-20
申请号：EP89303850.5
申请日：1989-04-19
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke , Kubosawa, Hajime
IPC分类号： G06F7/50
CPC分类号： G06F7/508 , G06F2207/4812
摘要： A binary operator comprises a plurality of carry select adder (CSA) circuits (101 a) each including a cumulative carry propagate signal generating means (106) and a cumulative carry generate signal generating means (107) and or a plurality of block look ahead carry generator (BLACG) circuits (105a) each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means (116) and a real carry signal generating means (117). The CSA circuit (101a) does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on the three signals of a carry propagate signal (P ; ), a cumulative carry propagate signal (BP i-1 *) and a cumulative carry generate signal (BG i-1 *) necessary for generating the presumed sum signal pair and the real carry signal (C M-1 ) to calculate the real sum signal (F i ). The BLACG circuit (105a) does not simultaneously generate two presumed carry signals and select and output one of the presumed carry signals, but uses a cumulative block carry propagate signal (CP M-1 *), a cumulative block carry generate signal (CG M-1 *) and a carry signal (C M '- m ') to directly generate the real carry signal (C M-1 ).
The number of circuit elements in such a binary operator is thereby greatly reduced without sacrificing high speed of computation since two presumed sum or carry signals are never generated in parallel.
摘要翻译：二进制运算符包括多个进位选择加法器（CSA）电路（101a），每个进位选择加法器（101a）包括累积进位传播信号产生装置（106）和累积进位产生信号产生装置（107）和/或多个前进块发生器（BLACG）电路（105a），每个包括累积块携带传播信号和累积块携带产生信号产生装置（116）和实际进位信号产生装置（117）。 CSA电路（101a）不同时产生两个推定的和信号，并选择并输出一个预测的和信号，而是直接对进位传播信号（Pi），累积进位传播信号（BPi- 1 *）和产生假定和信号对和实际进位信号（CM-1）所需的累积进位产生信号（BGi-1 *）以计算实和信号（Fi）。 BLACG电路（105a）不同时产生两个推定的进位信号，并选择并输出其中一个假设的进位信号，而是使用累积块进位传播信号（CPM-1 *），累积块进位生成信号（CGM-1 *）和进位信号（CM min -m min），以直接生成实际进位信号（CM-1）。这样的二进制运算符中的电路元件的数量因此大大降低，而不会牺牲高的计算速度，因为两个推定的和或进位信号不会并行产生。

5. 发明公开

EP0280257A1 Master slice type integrated circuit 失效
标题翻译： Integrierter Schaltkreis vom“Master slice”Typ。
公开(公告)号：EP0280257A1
公开(公告)日：1988-08-31
申请号：EP88102649.6
申请日：1988-02-23
申请人： FUJITSU LIMITED
发明人： Kubosawa, Hajime , Ishiguro, Masato
IPC分类号： H01L27/118
CPC分类号： H01L27/11807
摘要： A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprising a plurality of input/output cells (23) being arranged in a peripheral region on a semiconductor chip (20), a plurality of basic cell columns (22) each comprising a plurality of basic cells (21) arranged in a predetermined direction (A), each basic cell (21) constituting transistors, and an interconnection region (25) formed on the chip (20), for accommodating a data bus (55). The master slice type integrated circuit further comprises a plurality of latch cells (26) arranged in the basic cell columns (22), for keeping a potential of a data bus (55) laid on the interconnection region to prevent the data bus (55) from being changed into a floating state. Each latch cell (26) comprises transistors, each of which has a driving capability smaller than that of each transistor of the basic cell (21).
摘要翻译：一种主切片型集成电路，其中可以通过改变互连的路由来形成各种电路，包括布置在半导体芯片（20）上的周边区域中的多个输入/输出单元（23），多个基本单元每个包括沿预定方向（A）布置的多个基本单元（21）的列（22），构成晶体管的每个基本单元（21）和形成在芯片（20）上的互连区域（25），用于容纳数据总线（55）。主片式集成电路还包括布置在基本单元列（22）中的多个锁存单元（26），用于保持布置在互连区域上的数据总线（55）的电位以防止数据总线（55）从变成浮动状态。每个锁存单元（26）包括晶体管，每个晶体管的驱动能力小于基本单元（21）的每个晶体管的驱动能力。

6. 发明授权

EP0278463B1 Gate array having transistor buried in interconnection region 失效
标题翻译：门矩阵与在连接区域晶体管begrabenem。
公开(公告)号：EP0278463B1
公开(公告)日：1994-07-27
申请号：EP88101818.8
申请日：1988-02-08
申请人： FUJITSU LIMITED
发明人： Kubosawa, Hajime , Naitoh,Mitsugo
IPC分类号： H01L27/02 , H01L23/52
CPC分类号： H01L27/11807 , H01L23/535 , H01L2924/0002 , Y10S257/923 , H01L2924/00

7. 发明授权

EP0280257B1 Master slice type integrated circuit 失效
标题翻译：从“主切片”类型的集成电路。
公开(公告)号：EP0280257B1
公开(公告)日：1993-12-15
申请号：EP88102649.6
申请日：1988-02-23
申请人： FUJITSU LIMITED
发明人： Kubosawa, Hajime , Ishiguro, Masato
IPC分类号： H01L27/118
CPC分类号： H01L27/11807

8. 发明公开

EP0334768A3 Logic circuit having carry select adders 失效
标题翻译：具有携带选择添加物的逻辑电路
公开(公告)号：EP0334768A3
公开(公告)日：1991-11-06
申请号：EP89400856.4
申请日：1989-03-24
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke , Kubosawa, Hajime
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： An operation circuit for M-bit parallel full addition includes partitioned adders (11 - 21) and first and second multiplexers. Each of the first multiplexers (22 - 25) selects one of paired provisional carry signals C ns-1 (1) and C ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C (s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C ns-1 to be propagated from the s-th partitioned adder. Each of the second multiplexers (26 - 31) generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k = n(S + 1) - 1, n(s + 2) - 1, ..., n(s + ℓ) - 1) by referring to provisional carry signals Cr(1) (or Cr*(10; r = k - n = ns - 1) and Cr(0) (or Cr*(0); r = k - n = ns - 1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate ℓ real carry signals Ck at the same time by selecting either provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C (s-1)n-1 relating to a digit which is one digit lower than the lowest-order digit of the s-th partitioned adder.

9. 发明公开

EP0334768A2 Logic circuit having carry select adders 失效
标题翻译： Logikschaltung mit Uebertragungsgesteuerten Addierer。
公开(公告)号：EP0334768A2
公开(公告)日：1989-09-27
申请号：EP89400856.4
申请日：1989-03-24
申请人： FUJITSU LIMITED
发明人： Goto, Gensuke , Kubosawa, Hajime
IPC分类号： G06F7/50
CPC分类号： G06F7/507
摘要： An operation circuit for M-bit parallel full addition includes partitioned adders (11 - 21) and first and second multiplexers. Each of the first multiplexers (22 - 25) selects one of paired provisional carry signals C ns-1 (1) and C ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C (s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C ns-1 to be propagated from the s-th partitioned adder. Each of the second multiplexers (26 - 31) generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k = n(S + 1) - 1, n(s + 2) - 1, ..., n(s + ℓ) - 1) by referring to provisional carry signals Cr(1) (or Cr*(10; r = k - n = ns - 1) and Cr(0) (or Cr*(0); r = k - n = ns - 1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate ℓ real carry signals Ck at the same time by selecting either provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C (s-1)n-1 relating to a digit which is one digit lower than the lowest-order digit of the s-th partitioned adder.
摘要翻译：用于M位并行完全加法的操作电路包括分区加法器（11-21）和第一和第二多路复用器。每个第一多路复用器（22-25）根据实际进位信号C（的值）选择从第s个分割加法器提供的配对临时进位信号Cns-1（1）和Cns-1（0） s-1）n-1，所选择的一个临时进位信号是要从第s个分频加法器传播的实际进位信号Cns-1。每个第二复用器（26-31）产生一对临时进位信号Ck *（1）和Ck *（0）（k = n（S + 1）-1，n（s + 2）-1）。通过参考临时进位信号Cr（1）（或Cr *（10; r = k-n = ns-1）和Cr（0）（或Cr *（0）），n（s + 1））; r = k -n = ns-1），其比被生成的数字低n位，然后第二复用器通过选择临时进位信号Ck *（1）同时产生l个实际进位信号Ck，或Ck *（0），这取决于与第s分区加法器的最低位数字比一位低的数字的实际进位信号C（s-1）n-1。

10. 发明公开

EP0278463A2 Gate array having transistor buried in interconnection region 失效
标题翻译： Verbindungsgebiet begrabenem晶体管中的Gatematrix mit。
公开(公告)号：EP0278463A2
公开(公告)日：1988-08-17
申请号：EP88101818.8
申请日：1988-02-08
申请人： FUJITSU LIMITED
发明人： Kubosawa, Hajime , Naitoh,Mitsugo
IPC分类号： H01L27/02 , H01L23/52
CPC分类号： H01L27/11807 , H01L23/535 , H01L2924/0002 , Y10S257/923 , H01L2924/00
摘要： A gate array comprises a semiconductor substrate (40), a plurality of mutually parallel basic cell columns (41) each made up of a plurality of basic cells (44, 44X, 44Y) formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions (42, 42S) each formed between two mutually adjacent ones of the basic cell columns and specific cells (47, 47X, 60, 60X) buried in one or a plurality of predetermined ones (42S) of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor (P3) and a second n-channel transistor (N3) which constitute a transmission gate.
摘要翻译：栅极阵列包括半导体衬底（40），多个相互平行的基本单元列（41），每个基板单元由形成在半导体衬底上的多个基本单元（44,44,44Y）组成，其中每个基本单元包括一对第一p沟道晶体管和第一n沟道晶体管，每个形成在两个彼此相邻的基本单元列和特定单元（47,47X，60,60X）之间的多个互连区域（42,42S）埋置在互连区域的一个或多个预定的（42S）中，其中每个特定单元包括构成传输门的至少第二p沟道晶体管（P3）和第二n沟道晶体管（N3）。

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