专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP2480975B1 CONFIGURABLE CACHE FOR MULTIPLE CLIENTS 有权
公开(公告)号：EP2480975B1
公开(公告)日：2018-06-13
申请号：EP10819549.6
申请日：2010-09-24
申请人： Nvidia Corporation
发明人： MINKIN, Alexander L. , HEINRICH, Steven James , SELVANESAN, RaJeshwaran , COON, Brett W. , MCCARVER, Charles , RAJENDRAN, Anjana , CARLTON, Stewart G.
IPC分类号： G06F12/084
CPC分类号： G06F12/084 , G06F2212/2515 , G06F2212/301 , G06F2212/6012
摘要： One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A "direct mapped" storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A "local and global cache" storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.

2. 发明公开

EP3396556A1 ADAPTIVE CACHE SIZING PER WORKLOAD 审中-公开
公开(公告)号：EP3396556A1
公开(公告)日：2018-10-31
申请号：EP18159606.5
申请日：2018-03-01
申请人： INTEL Corporation
发明人： VEMBU, Balaji , KOKER, Altug , MASTRONARDE, Josh B. , KABURLASOS, Nikos , APPU, Abhishek R. , JAHAGIRDAR, Sanjeev S. , ASPERHEIM, Eric J. , MAIYURAN, Subramaniam , VEERNAPU, Kiran C. , K, Pattabhiraman , SINHA, Kamal , BOROLE, Bhushan M. , FU, Wenyin , RAY, Joydeep , SURTI, Prasoonkumar , HOEKSTRA, Eric J. , SCHLUESSLER, Travis T. , HURD, Linda L.
IPC分类号： G06F12/0895
CPC分类号： G06F12/0646 , G06F12/0895 , G06F2212/1028 , G06F2212/1044 , G06F2212/1048 , G06F2212/601 , G06F2212/6012 , G06F2212/604 , Y02D10/13
摘要： Briefly, in accordance with one or more embodiments, an apparatus comprises a processor to monitor cache utilization of an application during execution of the application for a workload; and a memory to store cache utilization statistics responsive to the monitored cache utilization. The processor is to determine an optimal cache configuration for the application based at least in part on the cache utilization statistics for the workload such that a smallest amount of cache is turned on for subsequent executions of the workload by the application.

3. 发明公开

EP2480975A1 CONFIGURABLE CACHE FOR MULTIPLE CLIENTS 有权
标题翻译：配置的缓存为多个客户
公开(公告)号：EP2480975A1
公开(公告)日：2012-08-01
申请号：EP10819549.6
申请日：2010-09-24
申请人： Nvidia Corporation
发明人： MINKIN, Alexander L. , HEINRICH, Steven James , SELVANESAN, RaJeshwaran , COON, Brett W. , MCCARVER, Charles , RAJENDRAN, Anjana , CARLTON, Stewart G.
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F2212/2515 , G06F2212/301 , G06F2212/6012
摘要： One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A "direct mapped" storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A "local and global cache" storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.

4. 发明公开

EP0999500A1 Application-reconfigurable split cache memory 审中-公开
标题翻译： Durch ein Anwendungsprogramm wiederkonfigurierbarer aufgeteilter Cache-Speicher
公开(公告)号：EP0999500A1
公开(公告)日：2000-05-10
申请号：EP99308403.7
申请日：1999-10-25
申请人： LUCENT TECHNOLOGIES INC.
发明人： Nicol, Christopher John , Singh, Kanwar Jit , Terman, Christopher J. , Williams, Joseph
IPC分类号： G06F12/08
CPC分类号： G06F12/0848 , G06F12/0853 , G06F2212/2515 , G06F2212/6012
摘要： Substantial advantages are realized from a processing element architecture that allows a local memory to be divided almost at will between an instruction cache portion, an instruction SRAM portion, a data SRAM portion, and a conventional data cache portion. The processing element comprises a processor and a memory module. The memory module comprises a plurality of memory submodules with associated interface circuitry, a controller, and at least one configuration register, which controls a particular memory submodule, is employed as an instruction submodule or a data submodule. In embodiments where there is a second configuration register, it controls whether a particular memory submodule is employed as a cache submodule or as an SRAM. Having the configuration registers addressable allows application programs to control the number of memory submodules that are assigned to different modes. In the illustrated embodiment, the processor can over-ride the SRAM/cache memory assignments of the configuration register. Providing a 2-port access, this architecture offers its advantages to Harvard-architecture processors.
摘要翻译：从处理元件架构实现了实质性的优点，该处理元件架构允许本地存储器几乎在指令高速缓存部分，指令SRAM部分，数据SRAM部分和常规数据高速缓存部分之间被分开。处理元件包括处理器和存储器模块。存储器模块包括具有相关接口电路的多个存储器子模块，控制器以及控制特定存储器子模块的至少一个配置寄存器，用作指令子模块或数据子模块。在存在第二配置寄存器的实施例中，它控制特定存储器子模块是否用作高速缓存子模块或作为SRAM。配置寄存器可寻址允许应用程序控制分配给不同模式的内存子模块的数量。在所示实施例中，处理器可以覆盖配置寄存器的SRAM /高速缓冲存储器分配。提供2端口访问，这种架构为哈佛架构处理器提供了优势。

5. 发明公开

EP3248106A1 DISTRIBUTED INDEX FOR FAULT TOLERANT OBJECT MEMORY FABRIC 审中-公开
标题翻译：分布式指令容错对象存储器结构
公开(公告)号：EP3248106A1
公开(公告)日：2017-11-29
申请号：EP16740661.0
申请日：2016-01-20
申请人： Ultrata LLC
发明人： FRANK, Steven , REBACK, Larry
IPC分类号： G06F13/00
CPC分类号： G06F3/0683 , G06F3/061 , G06F3/0631 , G06F3/0635 , G06F3/0638 , G06F3/064 , G06F3/0647 , G06F3/067 , G06F3/0685 , G06F12/0877 , G06F2212/6012
摘要： Embodiments of the invention provide systems and methods to implement an object memory fabric. Object memory modules may include object storage storing memory objects, memory object meta-data, and a memory module object directory. Each memory object and/or memory object portion may be created natively within the object memory module and may be a managed at a memory layer. The memory module object directory may index all memory objects and/or portions within the object memory module. A hierarchy of object routers may communicatively couple the object memory modules. Each object router may maintain an object cache state for the memory objects and/or portions contained in object memory modules below the object router in the hierarchy. The hierarchy, based on the object cache state, may behave in aggregate as a single object directory communicatively coupled to all object memory modules and to process requests based on the object cache state.

6. 发明公开

EP2480975A4 CONFIGURABLE CACHE FOR MULTIPLE CLIENTS 有权
标题翻译： KONFIGURIERBARER CACHEFÜRMEHRERE客户
公开(公告)号：EP2480975A4
公开(公告)日：2014-05-21
申请号：EP10819549
申请日：2010-09-24
申请人： NVIDIA CORP
发明人： MINKIN ALEXANDER L , HEINRICH STEVEN JAMES , SELVANESAN RAJESHWARAN , COON BRETT W , MCCARVER CHARLES , RAJENDRAN ANJANA , CARLTON STEWART G
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/084 , G06F2212/2515 , G06F2212/301 , G06F2212/6012
摘要： One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A "direct mapped" storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A "local and global cache" storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.
摘要翻译：本发明的一个实施例提出了一种用于提供作为中央存储资源的L1高速缓存的技术。 L1缓存为多个客户端提供不同的延迟和带宽要求。可以重新配置L1高速缓存以创建多个存储空间，使得L1高速缓存可以替代先前架构中的专用缓冲器，高速缓存和FIFO。配置在L1高速缓存内的“直接映射”存储区可以替代专用缓冲器，FIFO和接口路径，允许L1高速缓存的客户端交换属性和原始数据。直接映射存储区域可以用作全局寄存器文件。配置在L1高速缓存内的“本地和全局高速缓存”存储区域可用于支持向多个空间加载/存储存储器请求。这些空格包括全局，本地和回调栈（CRS）内存。

7. 发明公开

EP2251867A4 OPTICAL DISC DRIVE DEVICE 审中-公开
标题翻译：驱动装置的光盘
公开(公告)号：EP2251867A4
公开(公告)日：2012-09-05
申请号：EP09720630
申请日：2009-03-10
申请人： SHARP KK
发明人： UENO HIROYASU , FUJIWARA YASUHISA , IWATSUKI HIROYASU
IPC分类号： G11B20/10 , G11B7/004
CPC分类号： G11B7/28 , G06F3/0608 , G06F3/0611 , G06F3/0656 , G06F3/0677 , G06F3/068 , G06F12/0873 , G06F2212/211 , G06F2212/214 , G06F2212/2146 , G06F2212/217 , G06F2212/222 , G06F2212/6012 , G11B20/10527 , G11B2007/0006 , G11B2020/10759 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562

8. 发明公开

EP3106992A1 APPARATUS AND METHOD FOR PERFORMING CACHE MANAGEMENT IN A STORAGE SYSTEM 审中-公开
标题翻译：装置和方法缓存内存管理在存储系统实现
公开(公告)号：EP3106992A1
公开(公告)日：2016-12-21
申请号：EP16172821.7
申请日：2016-06-03
申请人： Synology Incorporated
发明人： Lin, Yi-Chun , Liang, Chih-Cheng , Wang, Yu-Ting , Chen, Hsuan-Ting
IPC分类号： G06F12/0804 , G06F12/0862 , G06F12/0868 , G06F12/0871
CPC分类号： G06F3/0683 , G06F3/0604 , G06F3/0638 , G06F12/0804 , G06F12/0862 , G06F12/0868 , G06F12/0871 , G06F12/0886 , G06F2212/1044 , G06F2212/262 , G06F2212/6012 , G06F2212/603
摘要： A method (300) for performing cache management for a storage system (100) and an associated apparatus are provided, where the storage system (100) includes a plurality of storage devices. The method (300) includes: utilizing a storage device (120-1) of the plurality of storage devices as a cache (122) of another storage device of the plurality of storage devices, in which an access speed of the storage device is higher than that of the other storage device, and the cache (122) includes a plurality of cache blocks; and when a read miss of the cache (122) occurs, reading data corresponding to at least one cache block from the other storage device to store the data into the cache (122), in which a data amount corresponding to the read miss is less than a data amount of each cache block of the plurality of cache blocks.
摘要翻译：本发明提供一种用于存储系统（100）和相关联装置进行高速缓存管理方法（300），其中所述存储系统（100）包括存储设备的复数。该方法（300）包括：利用存储装置的多个存储装置（120-1），其存储设备的多个另一存储装置的高速缓存（122），其中，以访问存储设备的速度较高比其他存储设备，并且所述高速缓存（122）包括高速缓存块中的多个; 并且当所述高速缓存（122）上出现的一读未命中，readingdata从其他存储装置对应于至少一个高速缓存块将数据存储到高速缓冲存储器（122），其中的数据量对应于所述读取未命中是少比高速缓存块的所述多个每个高速缓存块的数据量。

9. 发明公开

EP1967946A3 Method of converting a hybrid hard disk drive to a normal HDD 审中-公开
标题翻译：在一个正常的硬盘驱动器转换混合硬盘驱动器的方法
公开(公告)号：EP1967946A3
公开(公告)日：2013-04-03
申请号：EP08152429.0
申请日：2008-03-07
申请人： Samsung Electronics Co., Ltd.
发明人： Nam, Hye-jeong , Lee, Jae-sung
IPC分类号： G06F3/06 , G06F11/07
CPC分类号： G06F3/0634 , G06F3/0614 , G06F3/0632 , G06F3/0674 , G06F3/068 , G06F12/0866 , G06F2212/217 , G06F2212/6012 , G06F2212/7204
摘要： A method of converting a hybrid hard disk drive (HDD) to a normal HDD when a system is powered on depending on whether the total number of defective blocks in a non-volatile cache (NVC) exceeds a predetermined threshold. The method of converting a hard disk drive (HDD) from a hybrid HDD to a normal HDD where the HDD has a normal hard disk and a non-volatile cache includes the steps of determining whether a mode conversion flag is enabled during a power-on period. When the mode conversion flag is enabled, operating the HDD as a normal HDD. When the mode conversion flag is disabled, determining whether an operating mode of the HDD is a normal mode or a hybrid mode. When the operating mode of the HDD is the normal mode, the HDD operates as a normal HDD. A determination is made when the HDD is in the hybrid mode as to whether the total number of defective blocks in the non-volatile cache is greater than a predetermined threshold. The HDD is operated as a hybrid HDD when the total number of defective blocks is not greater than the threshold. The mode conversion flag is enabled and the HDD is operated as a hybrid HDD when the total number of defective blocks is greater than the threshold.

10. 发明公开

EP2251867A1 OPTICAL DISC DRIVE DEVICE 审中-公开
标题翻译： ANTRIEBSVORRICHTUNGFÜREINE OPTISCHE PLATTE
公开(公告)号：EP2251867A1
公开(公告)日：2010-11-17
申请号：EP09720630.4
申请日：2009-03-10
申请人： Sharp Kabushiki Kaisha
发明人： UENO, Hiroyasu , FUJIWARA, Yasuhisa , IWATSUKI, Hiroyasu
IPC分类号： G11B20/10 , G11B7/004
CPC分类号： G11B7/28 , G06F3/0608 , G06F3/0611 , G06F3/0656 , G06F3/0677 , G06F3/068 , G06F12/0873 , G06F2212/211 , G06F2212/214 , G06F2212/2146 , G06F2212/217 , G06F2212/222 , G06F2212/6012 , G11B20/10527 , G11B2007/0006 , G11B2020/10759 , G11B2220/2541 , G11B2220/2545 , G11B2220/2562
摘要： A hybrid BD drive 1 (1) of the present invention includes a flash control section (2) which (a) uses a flash memory (7) as a cache memory in a case where the hybrid BD drive (1) receives an address or data via an interface (13) and which (b) uses the flash memory (7) as a data memory in a case where the hybrid BD drive (1) receives an address or data via an interface (14). This makes it possible to provide an optical disc drive device having a nonvolatile memory capable of reducing an access time in random access and storing data except cache data.
摘要翻译：本发明的混合BD驱动器1（1）包括闪光控制部分（2），其中（a）在混合BD驱动器（1）接收地址的情况下使用闪速存储器（7）作为高速缓冲存储器，在混合BD驱动器（1）经由接口（14）接收地址或数据的情况下，经由接口（13）的数据和（b）使用闪速存储器（7）作为数据存储器。这使得可以提供一种具有非易失性存储器的光盘驱动装置，该非易失性存储器能够减少随机存取中的访问时间并存储除高速缓存数据之外的数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式