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1. 发明公开

EP2480975A4 CONFIGURABLE CACHE FOR MULTIPLE CLIENTS 有权
标题翻译： KONFIGURIERBARER CACHEFÜRMEHRERE客户
公开(公告)号：EP2480975A4
公开(公告)日：2014-05-21
申请号：EP10819549
申请日：2010-09-24
申请人： NVIDIA CORP
发明人： MINKIN ALEXANDER L , HEINRICH STEVEN JAMES , SELVANESAN RAJESHWARAN , COON BRETT W , MCCARVER CHARLES , RAJENDRAN ANJANA , CARLTON STEWART G
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/084 , G06F2212/2515 , G06F2212/301 , G06F2212/6012
摘要： One embodiment of the present invention sets forth a technique for providing a L1 cache that is a central storage resource. The L1 cache services multiple clients with diverse latency and bandwidth requirements. The L1 cache may be reconfigured to create multiple storage spaces enabling the L1 cache may replace dedicated buffers, caches, and FIFOs in previous architectures. A "direct mapped" storage region that is configured within the L1 cache may replace dedicated buffers, FIFOs, and interface paths, allowing clients of the L1 cache to exchange attribute and primitive data. The direct mapped storage region may used as a global register file. A "local and global cache" storage region configured within the L1 cache may be used to support load/store memory requests to multiple spaces. These spaces include global, local, and call-return stack (CRS) memory.
摘要翻译：本发明的一个实施例提出了一种用于提供作为中央存储资源的L1高速缓存的技术。 L1缓存为多个客户端提供不同的延迟和带宽要求。可以重新配置L1高速缓存以创建多个存储空间，使得L1高速缓存可以替代先前架构中的专用缓冲器，高速缓存和FIFO。配置在L1高速缓存内的“直接映射”存储区可以替代专用缓冲器，FIFO和接口路径，允许L1高速缓存的客户端交换属性和原始数据。直接映射存储区域可以用作全局寄存器文件。配置在L1高速缓存内的“本地和全局高速缓存”存储区域可用于支持向多个空间加载/存储存储器请求。这些空格包括全局，本地和回调栈（CRS）内存。

2. 发明公开

EP2480985A4 UNIFIED ADDRESSING AND INSTRUCTIONS FOR ACCESSING PARALLEL MEMORY SPACES 有权
标题翻译：统一编址以及访问并行存储空间的说明
公开(公告)号：EP2480985A4
公开(公告)日：2014-04-23
申请号：EP10819552
申请日：2010-09-24
申请人： NVIDIA CORP
发明人： NICKOLLS JOHN R , COON BRETT W , BUCK IAN A , GLANVILLE ROBERT STEVEN
IPC分类号： G06F12/02 , G06F12/10 , G06F15/167
CPC分类号： G06F12/1054 , G06F12/0284 , G06F12/109 , G06F13/404 , G06F2212/302 , G06F2212/656
摘要： One embodiment of the present invention sets forth a technique for unifying the addressing of multiple distinct parallel memory spaces into a single address space for a thread. A unified memory space address is converted into an address that accesses one of the parallel memory spaces for that thread. A single type of load or store instruction may be used that specifies the unified memory space address for a thread instead of using a different type of load or store instruction to access each of the distinct parallel memory spaces.

3. 发明公开

EP2483772A4 TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT 有权
标题翻译：故障排除体系FOR A并行处理单元
公开(公告)号：EP2483772A4
公开(公告)日：2014-04-02
申请号：EP10821124
申请日：2010-09-28
申请人： NVIDIA CORP
发明人： SHEBANOW MICHAEL C , CHOQUETTE JACK , COON BRETT W , HEINRICH STEVEN J , KALAIAH ARAVIND , NICKOLLS JOHN R , SALINAS DANIEL , SIU MING , THORN TOMMY , WANG NICHOLAS
IPC分类号： G06F9/38 , G06F9/32
CPC分类号： G06F9/327 , G06F9/3851 , G06F9/3861

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