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    • 8. 发明公开
    • DTC-BASED PLL AND METHOD FOR OPERATING THE DTC-BASED PLL
    • 基于DTC的PLL和用于操作基于DTC的PLL的方法
    • EP3249817A1
    • 2017-11-29
    • EP17172898.3
    • 2017-05-24
    • IMEC vzwStichting IMEC NederlandVrije Universiteit Brussel
    • MARKULIC, NereoLIU, Yao-HongCRANINCKX, Jan
    • H03L7/197H03L7/081H03L7/099
    • H03L7/085H03K5/159H03K2005/00013H03L7/081H03L7/0991H03L7/197H03L7/1976H03L2207/50
    • The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator generating the output signal based on at least a phase difference between reference and feedback signal, a digital-to-time converter, DTC, delaying a signal that is provided at one of the first and second input, a delay calculation path for calculating a DTC delay value. The PLL further comprises a randomization unit for generating and adding a stream of pseudo-random offsets, i.e. pseudo-random numbers, to the delay value. The offset is such that the target output of the phase detector remains substantially unchanged.
    • 本公开提供了一种锁相环PLL,用于将输出信号锁相到参考信号。 PLL包括将参考信号提供给相位检测器的第一输入端的参考路径,将PLL的输出信号作为反馈信号提供给相位检测器的第二输入端的反馈回路,基于相位检测器产生输出信号的可控制振荡器 至少在参考和反馈信号之间的相位差上,数字 - 时间转换器DTC延迟在第一和第二输入之一提供的信号,延迟计算路径用于计算DTC延迟值。 该PLL还包括一个随机化单元,用于产生一个伪随机偏移流,即伪随机数,并将其添加到该延迟值。 偏移量使得相位检测器的目标输出保持基本不变。
    • 10. 发明公开
    • Circuit for digitizing a sum of signals
    • Schallung zur Digitalisierung einer Summe von Signalen
    • EP2706666A1
    • 2014-03-12
    • EP12183714.0
    • 2012-09-10
    • IMECStichting IMEC NederlandKatholieke Universiteit Leuven
    • Morgado, AlonsoPorrzzo, SerenaCannillo Francesco
    • H03M3/04
    • H03M3/32H03M3/426H03M3/452
    • The present invention relates to a circuit for digitizing a sum of at least one first input signal and a plurality of second input signals comprising
      - a passive adder circuit arranged for performing a summation of the second input signals and for outputting a summation signal,
      - a multi-bit quantizer circuit comprising a comparator arranged for comparing said summation signal applied at a first comparator input terminal with a signal applied at a second comparator input terminal, said signal being derived from the at least one first input signal and having an appropriate polarity so that the difference between the summation signal and said signal at the second comparator input terminal is indicative of the sum of the at least one first input signal and the plurality of second input signals, wherein the comparator is further arranged for producing a comparator output signal based on the sum of the at least one first input signal and the plurality of second input signals. The multi-bit quantizer circuit further comprises a control logic block for determining a multi-bit representation of the sum from the comparator output signal.
    • 本发明涉及一种用于数字化至少一个第一输入信号和多个第二输入信号的和的电路,包括:被动加法器电路,被配置为执行第二输入信号的求和并输出求和信号, - 一 多比特量化器电路,包括比较器,用于将在第一比较器输入端施加的所述求和信号与施加在第二比较器输入端的信号进行比较,所述信号从至少一个第一输入信号导出,并具有适当的极性 第二比较器输入端的求和信号和所述信号之间的差表示至少一个第一输入信号和多个第二输入信号之和,其中该比较器进一步被布置用于产生基于比较器输出信号的比较器输出信号 在所述至少一个第一输入信号和所述多个第二输入信号的和之间。 多比特量化器电路还包括用于确定来自比较器输出信号的和的多位表示的控制逻辑块。