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1. 发明授权

EP0771105B1 Clock re-timing apparatus with cascaded delay stages 失效
标题翻译：一种用于时钟信号同步地通过级联延时级的装置
公开(公告)号：EP0771105B1
公开(公告)日：2013-09-25
申请号：EP96116666.7
申请日：1996-10-17
申请人： THOMSON CONSUMER ELECTRONICS, INC.
发明人： Rumreich, Mark Francis , Gyurek, John William
IPC分类号： H04N5/073 , H04N5/45 , H03L7/00
CPC分类号： H03L7/00 , H03K5/15046 , H04N5/04 , H04N5/45

2. 发明公开

EP0771105A2 Clock re-timing apparatus with cascaded delay stages 失效
标题翻译：一种用于时钟信号同步地通过级联延时级的装置
公开(公告)号：EP0771105A2
公开(公告)日：1997-05-02
申请号：EP96116666.7
申请日：1996-10-17
申请人： THOMSON CONSUMER ELECTRONICS, INC.
发明人： Rumreich, Mark Francis , Gyurek, John William
IPC分类号： H04N5/073
CPC分类号： H03L7/00 , H03K5/15046 , H04N5/04 , H04N5/45
摘要： A video clock input signal (MCK) is applied to a delay line (30) comprising a cascade connection of a plurality (T1-T19) of delay elements for providing a plurality of delayed clock signals at respective taps (T1-T15) of the delay line. A selection circuit (6), responsive to a horizontal synchronizing signal (HS) supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal (YCK) that is edge-aligned with the synchronizing signal (HS). For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group (T1-T13) of the delay elements and are spaced more than one element apart for at least one (T13-T16; T17-T18; T19) second group of the elements.

3. 发明公开

EP0596435A1 Automatic test clock selection apparatus 失效
标题翻译： Schaltungfürautomatische Test-Taktsignalanwahl。
公开(公告)号：EP0596435A1
公开(公告)日：1994-05-11
申请号：EP93117659.8
申请日：1993-11-02
申请人： THOMSON CONSUMER ELECTRONICS, INC.
发明人： Albean, David Lawrence , Gyurek, John William , Duncan, Christopher Dale
IPC分类号： H03K5/26 , G01R31/28
CPC分类号： H03K5/26 , G01R31/3016 , G01R31/31701 , G01R31/318328 , G01R31/31922
摘要： An integrated circuit (100) includes circuitry for generating a clock signal (CLOCK) during both a normal mode of operation and a test mode of operation. During the normal mode, an input clock signal is delayed via a skew corrector (135). In test mode, an input test clock signal (TEST CLOCK) bypasses the skew corrector (135) via a clock signal source selector (150). The clock signal source selector (150) is controlled automatically by a mode detector (140) that responds to the input clock signals to determine the mode of operation of the integrated circuit (100).
摘要翻译：集成电路（100）包括用于在正常操作模式和测试操作模式期间产生时钟信号（CLOCK）的电路。在正常模式期间，经由偏斜校正器（135）延迟输入时钟信号。在测试模式中，输入测试时钟信号（TEST CLOCK）经由时钟信号源选择器（150）绕过歪斜校正器（135）。时钟信号源选择器（150）由响应输入时钟信号的模式检测器（140）自动控制，以确定集成电路（100）的工作模式。

4. 发明公开

EP0771105A3 Clock re-timing apparatus with cascaded delay stages 失效
标题翻译： Vorrichtung zur Taktsignalsynchronisierung mittels kaskadierterVerzögerungsstufen
公开(公告)号：EP0771105A3
公开(公告)日：1999-06-09
申请号：EP96116666.7
申请日：1996-10-17
申请人： THOMSON CONSUMER ELECTRONICS, INC.
发明人： Rumreich, Mark Francis , Gyurek, John William
IPC分类号： H04N5/073
CPC分类号： H03L7/00 , H03K5/15046 , H04N5/04 , H04N5/45
摘要： A video clock input signal (MCK) is applied to a delay line (30) comprising a cascade connection of a plurality (T1-T19) of delay elements for providing a plurality of delayed clock signals at respective taps (T1-T15) of the delay line. A selection circuit (6), responsive to a horizontal synchronizing signal (HS) supplied thereto, couples a selected one of the taps to an output for providing a delayed output clock signal (YCK) that is edge-aligned with the synchronizing signal (HS). For reducing the number of taps required to provide a given minimum delay step resolution and a given minimum total delay for delay elements which may vary in delay, from one integrated circuit to another, the taps are spaced one element apart for a first group (T1-T13) of the delay elements and are spaced more than one element apart for at least one (T13-T16; T17-T18; T19) second group of the elements.
摘要翻译：视频时钟输入信号（MCK）被施加到包括多个（T1-T19）延迟元件的级联连接的延迟线（30），用于在相应的抽头（T1-T15）上提供多个延迟的时钟信号延迟线。选择电路（6）响应于提供给其的水平同步信号（HS），将选择的一个抽头耦合到输出端，以提供与同步信号（HS）边缘对准的延迟输出时钟信号（YCK））。为了减少提供给定的最小延迟步长分辨率所需的抽头数量以及延迟元件给定的最小总延迟数，这些延迟元件可能随时间而变化，从一个集成电路到另一个集成电路，对于第一组（T1 -T13），并且对于至少一个（T13-T16; T17-T18; T19）第二组元件而间隔多于一个元件。

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