专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP0379289A3 Fixture and a method for plating contact bumps for integrated circuits 失效
标题翻译：用于集成电路的接触焊料的固定和方法
公开(公告)号：EP0379289A3
公开(公告)日：1990-08-01
申请号：EP90300208.7
申请日：1990-01-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Stierman, Roger J. , Lessard, Robert J.
IPC分类号： C25D7/12
CPC分类号： C25D17/06 , C25D7/12 , H01L21/67138 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/14
摘要： @ This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer (11) is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterned by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode (3) is located directly above the wafer (11). Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.

2. 发明公开

EP0587442A2 Wire bonding over the active circuit area of an integrated circuit device 失效
标题翻译： üenüüüüiven。。。。。。。。。。。。。。
公开(公告)号：EP0587442A2
公开(公告)日：1994-03-16
申请号：EP93307165.6
申请日：1993-09-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Heinen, Katherine G. , Alfaro,Rafael Verity Instruments Inc. , Stierman, Roger J.
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/04042 , H01L2224/05093 , H01L2224/05624 , H01L2224/451 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/78 , H01L2224/85099 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/20102 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20305 , H01L2924/20309 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Wire bonding over the active circuit (13) of an integrated circuit device (10) is accomplished by providing a layer of a polyimide material (23) in overlying relationship relative to the active circuit, depositing a bonding pad (31) on the polyimide layer opposite the active circuit, connecting the bonding pad electrically to the active circuit, and bonding a wire (33) to the bonding pad.
摘要翻译：集成电路器件（10）的有源电路（13）上的引线接合通过以相对于有源电路为重叠的关系提供一层聚酰亚胺材料（23）来实现，在聚酰亚胺层上沉积焊盘（31）与有源电路相对，将焊盘电连接到有源电路，并将导线（33）接合到接合焊盘。

3. 发明公开

EP1139396A3 Fixture and method for uniform electroless metal deposition on integrated circuit bond pads 审中-公开
标题翻译：在集成电路上的焊盘保持均匀电金属沉积的装置和方法
公开(公告)号：EP1139396A3
公开(公告)日：2003-08-27
申请号：EP01000047.9
申请日：2001-03-09
申请人： Texas Instruments Incorporated
发明人： Amador, Gonzalo , Stierman, Roger J.
IPC分类号： H01L21/288 , H01L21/00
CPC分类号： H01L21/288 , C23C18/1619 , C23C18/1669 , H01L24/02 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2924/00011 , H01L2924/01004 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers (101), and rotating each wafer at constant speed and synchronously within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniform layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

4. 发明授权

EP0379289B1 Fixture and a method for plating contact bumps for integrated circuits 失效
标题翻译：保持装置和方法用于镀覆驼峰形端子为集成电路。
公开(公告)号：EP0379289B1
公开(公告)日：1995-04-19
申请号：EP90300208.7
申请日：1990-01-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Stierman, Roger J. , Lessard, Robert J.
IPC分类号： C25D7/12
CPC分类号： C25D17/06 , C25D7/12 , H01L21/67138 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/14

5. 发明公开

EP1139396A2 Fixture and method for uniform electroless metal deposition on integrated circuit bond pads 审中-公开
标题翻译：在集成电路上的焊盘保持均匀电金属沉积的装置和方法
公开(公告)号：EP1139396A2
公开(公告)日：2001-10-04
申请号：EP01000047.9
申请日：2001-03-09
申请人： Texas Instruments Incorporated
发明人： Amador, Gonzalo , Stierman, Roger J.
IPC分类号： H01L21/288 , H01L21/00
CPC分类号： H01L21/288 , C23C18/1619 , C23C18/1669 , H01L24/02 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2924/00011 , H01L2924/01004 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.
摘要翻译：如结合垫：一种用于在层中的均匀的无电解镀到在集成电路金属化露出的方法和装置。该装置提供了用于固定晶片的多个，并且每个晶片在所述多个内恒定的速度和同步旋转。在以基本为层运动，并在恒定的速度流动的电镀液浸入，该方法创建的方向和晶片的运动和电镀液的运动的速度的周期叠加。该发明创建周期性变化的晶片部分，其中的方向和速度是添加剂和其中方向和速度相对并消减。因此，高度一致的层无电电镀到键合焊盘的暴露的金属化。如果镀覆层是可焊接的金属，则处理转换否则unbondable焊盘金属化到粘合的垫。

6. 发明公开

EP1126519A2 Structure and method for bond pads of copper-metallized intergrated circuits 审中-公开
标题翻译： Struktur und Herstellungsmethode vonAnschlussflächenauf verkupferten intergrierten Schaltungen
公开(公告)号：EP1126519A2
公开(公告)日：2001-08-22
申请号：EP01000021.4
申请日：2001-02-19
申请人： Texas Instruments Incorporated
发明人： Stierman, Roger J. , Amador, Gonzalo , Test, Howard R.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/0518 , H01L2224/05184 , H01L2224/05556 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4845 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/78301 , H01L2224/85043 , H01L2224/85045 , H01L2224/85201 , H01L2224/85205 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/3025 , H01L2924/00014 , H01L2924/01004 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2224/29099 , H01L2924/00015 , H01L2924/013
摘要： A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1 x 10E-23 cm 2 /s at 250 °C and a thickness from about 0.5 to 1.5 µm. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1 x 10E-14 cm 2 /s at 250 °C and a thickness of less than 1.5 µm. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection.
The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost metal layer is selected from a group consisting of gold, platinum, and silver.
摘要翻译：坚固，可靠和低成本的金属结构和工艺，使电线/带连接到集成电路的互连铜金属化。该结构包括沉积在非氧化铜表面上的第一阻挡金属层，其铜扩散系数在250℃下小于1×10E-23cm 2 / s，厚度为约0.5至1.5 亩它还包括在第一阻挡金属层上的第二阻挡金属层，其在250℃下的第一阻挡金属的扩散系数小于1×10E-14cm 2 / s，并且厚度小于 1.5亩它最后包括可粘结金属的最外层，金属丝被粘合在其上用于冶金连接。第一阻挡金属选自镍，钴，铬，钼，钛，钨及其合金。第二阻挡金属选自钯，钴，铂和锇。最外面的金属层选自金，铂和银。

7. 发明公开

EP1126519A3 Structure and method for bond pads of copper-metallized intergrated circuits 审中-公开
标题翻译：对intergrierten电路镀铜垫结构和制造方法
公开(公告)号：EP1126519A3
公开(公告)日：2004-02-18
申请号：EP01000021.4
申请日：2001-02-19
申请人： Texas Instruments Incorporated
发明人： Stierman, Roger J. , Amador, Gonzalo , Test, Howard R.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/53228 , H01L23/53233 , H01L23/53238 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05082 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05157 , H01L2224/05164 , H01L2224/05166 , H01L2224/0518 , H01L2224/05184 , H01L2224/05556 , H01L2224/05639 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4845 , H01L2224/48463 , H01L2224/48639 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/48739 , H01L2224/48764 , H01L2224/48769 , H01L2224/48839 , H01L2224/48844 , H01L2224/48864 , H01L2224/78301 , H01L2224/85043 , H01L2224/85045 , H01L2224/85201 , H01L2224/85205 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/19043 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20108 , H01L2924/20109 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/3025 , H01L2924/00014 , H01L2924/01004 , H01L2924/00 , H01L2224/48869 , H01L2224/48744 , H01L2224/29099 , H01L2924/00015 , H01L2924/013
摘要： A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of first barrier metal, deposited on the non-oxidized copper surface, having a copper diffusion coefficient of less than 1 x 10E-23 cm 2 /s at 250 °C and a thickness from about 0.5 to 1.5 µm. It further comprises a layer of second barrier metal on the layer of first barrier metal, having a diffusion coefficient of the first barrier metal of less than 1 x 10E-14 cm 2 /s at 250 °C and a thickness of less than 1.5 µm. It finally comprises an outermost layer of bondable metal, onto which a metal wire is bonded for metallurgical connection. The first barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The second barrier metal is selected from a group consisting of palladium, cobalt, platinum and osmium. The outermost metal layer is selected from a group consisting of gold, platinum, and silver.

9. 发明公开

EP0587442A3 Wire bonding over the active circuit area of an integrated circuit device 失效
标题翻译：在集成电路器件的有源电路区域上进行引线键合
公开(公告)号：EP0587442A3
公开(公告)日：1994-08-03
申请号：EP93307165.6
申请日：1993-09-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Heinen, Katherine G. , Alfaro,Rafael Verity Instruments Inc. , Stierman, Roger J.
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/04042 , H01L2224/05093 , H01L2224/05624 , H01L2224/451 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/78 , H01L2224/85099 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/14 , H01L2924/181 , H01L2924/20102 , H01L2924/20105 , H01L2924/20106 , H01L2924/20107 , H01L2924/20305 , H01L2924/20309 , H01L2924/30105 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Wire bonding over the active circuit (13) of an integrated circuit device (10) is accomplished by providing a layer of a polyimide material (23) in overlying relationship relative to the active circuit, depositing a bonding pad (31) on the polyimide layer opposite the active circuit, connecting the bonding pad electrically to the active circuit, and bonding a wire (33) to the bonding pad.
摘要翻译：集成电路器件（10）的有源电路（13）上的引线键合是通过提供相对于有源电路成叠置关系的聚酰亚胺材料层（23），在聚酰亚胺层上沉积键合焊盘（31）与有源电路相对，将键合焊盘电连接到有源电路，以及将导线（33）键合到键合焊盘。

10. 发明公开

EP0379289A2 Fixture and a method for plating contact bumps for integrated circuits 失效
标题翻译：保持装置和方法用于镀覆驼峰形端子为集成电路。
公开(公告)号：EP0379289A2
公开(公告)日：1990-07-25
申请号：EP90300208.7
申请日：1990-01-09
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Stierman, Roger J. , Lessard, Robert J.
IPC分类号： C25D7/12
CPC分类号： C25D17/06 , C25D7/12 , H01L21/67138 , H01L24/11 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/14
摘要： @ This disclosure describes a plating fixture to hold a silicon wafer containing integrated circuits in a metal plating bath. The wafer (11) is coated with photoresist to a thickness equal to the desired bump height and the desired bump locations patterned by standard photolithographic techniques. The wafer is then loaded in the fixture and the fixture placed in the plating bath so that the patterned side of the wafer is facing up and the plating anode (3) is located directly above the wafer (11). Systems presently on the market have the wafer positioned with the patterned side facing down and the anode located below it, or the wafer faces sideways and the anodes are access from it. These present systems allow air to be entrapped in the pattern of the photoresist, lowering yield by under plating or uneven plating of the bumps on the wafer. This disclosure prevents such yield loss and also allows cleanups on the wafer after it is loaded in the fixture.
摘要翻译：本发明描述一种电镀夹具保持容纳集成电路的金属镀浴的硅晶片。晶片（11）涂覆有光刻胶的厚度等于期望凸块高度，并通过标准的光刻技术构图所需的凸块的位置。然后将晶片装载到夹具和在镀浴中放置在夹具所以没有晶片的图案的一面朝上和电镀阳极（3）直接位于所述晶片（11）的上方。系统目前市场上有图案化的面朝下，位于其下方的阳极位于晶片，或晶片面向侧向和阳极是从它的访问。这些本发明的系统允许空气在光致抗蚀剂的图案来截留，降低下电镀或晶片上的凸块的不均匀的电镀产生通过。本发明防止了寻求的产率损失，并且因此它被加载到夹具后允许在晶片上的清理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式