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1. 发明公开

EP2843674A1 Dye-sensitized solar cell, tandem dye-sensitized solar cell, and composite nanostructure 审中-公开
标题翻译： Farbstoffsensibilisierte Solarzelle，farbstoffsensibilisierte Tandemsolarzelle und Verbundnanostruktur
公开(公告)号：EP2843674A1
公开(公告)日：2015-03-04
申请号：EP14002948.9
申请日：2014-08-25
申请人： Sharp Kabushiki Kaisha
发明人： Lee, Jong-Jan , Nishimura, Karen Yuri , Pan, Wei , Vail, Sean Andrew
IPC分类号： H01G9/20 , H01L51/42
CPC分类号： H01G9/2036 , H01G9/2072 , H01L51/4226 , Y02E10/542 , Y02E10/549
摘要： A dye-sensitized solar cell (DSC) (400) is provided, made from an anode layer (406) of tin oxide (SnO 2 ) coated titanium oxide (TiO 2 ) nanostructures (300) that overlie a substrate (402) top surface (404). A dye (407) overlies the anode layer (406), and a cathode (408) overlies the dye (407). The cathode (408) may be a hole conducting layer having a solid state phase or a redox electrolyte, with a counter electrode (412). The TiO 2 nanostructures (300) may be TiO 2 nanoparticles, TiO 2 nanowires, or TiO 2 nanotubes. In the case of TiO 2 nanowires or TiO 2 nanotubes, their center axes (500) are perpendicular to the substrate (402) top surface (404). Regardless of the TiO 2 nanostructure (300) morphology, the SnO 2 coating (304) thickness (306) is in the range of 2 to 10 nanometers (nm). In one aspect, the SnO 2 coated TiO 2 nanostructures (300) have a dielectric layer shell (308), which may have a thickness (310) in the range of 0.3 to 2 nm.
摘要翻译：提供染料敏化太阳能电池（DSC）（400），其由覆盖在基板（402）上表面上的氧化锡（SnO 2）涂覆的氧化钛（TiO 2）纳米结构（300）的阳极层（406）（404）。染料（407）覆盖阳极层（406），阴极（408）覆盖染料（407）。阴极（408）可以是具有固态相或氧化还原电解质的空穴传导层，具有对电极（412）。 TiO 2纳米结构（300）可以是TiO 2纳米颗粒，TiO 2纳米线或TiO 2纳米管。在TiO 2纳米线或TiO 2纳米管的情况下，它们的中心轴线（500）垂直于衬底（402）顶表面（404）。不管TiO 2纳米结构（300）形态如何，SnO 2涂层（304）厚度（306）在2至10纳米（nm）的范围内。在一个方面，SnO 2涂覆的TiO 2纳米结构（300）具有介电层壳（308），其可以具有在0.3至2nm范围内的厚度（310）。

2. 发明授权

EP1441391B1 Dual-trench isolated crosspoint memory array and method for fabricating same 有权转让
标题翻译：双严重孤立的交叉点存储器阵列及其制造方法
公开(公告)号：EP1441391B1
公开(公告)日：2008-11-26
申请号：EP03258165.4
申请日：2003-12-24
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei
IPC分类号： H01L27/10
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101 , H01L27/24

3. 发明公开

EP1511085A3 Asymmetric crystalline structure memory cell 有权转让
标题翻译：具有不对称晶体结构的存储单元
公开(公告)号：EP1511085A3
公开(公告)日：2006-03-22
申请号：EP04011964.6
申请日：2004-05-19
申请人： SHARP KABUSHIKI KAISHA
发明人： HSU, Sheng Teng , Li, Tingkai , Evans, David Russell , Zhuang, Wei-Wei , Pan, Wei
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1625
摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.

4. 发明公开

EP1369501A3 Preparation of LCPMO thin films which have reversible resistance change properties 审中-公开
标题翻译：薄膜的生产与LCPMO reversibelen电阻变化特性
公开(公告)号：EP1369501A3
公开(公告)日：2005-10-12
申请号：EP03253093.3
申请日：2003-05-16
申请人： SHARP KABUSHIKI KAISHA
发明人： Zhuang, Weiwei , HSU, Sheng Teng , Pan, Wei , Tajiri, Masayuki
IPC分类号： C23C18/12 , H01L21/316
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1283 , G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90°C to 300°C; and annealing the coated substrate at a temperature of between about 500°C to 800°C for between about five minutes to fifteen minutes.

5. 发明授权

EP1403920B1 Method of fabricating self-aligned cross-point memory array 有权
标题翻译：一种制造自对准的交叉点存储器阵列的方法
公开(公告)号：EP1403920B1
公开(公告)日：2009-09-23
申请号：EP03254924.8
申请日：2003-08-07
申请人： Sharp Kabushiki Kaisha
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei
IPC分类号： H01L21/8246 , H01L27/10
CPC分类号： H01L27/24 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101

6. 发明公开

EP1507297A3 Method for obtaining reversible resistance switches in a PCMO thin film deposited on a highly crystallized seed layer 有权
标题翻译：一种用于在沉积在高度结晶种子层上的PCMO薄膜的可逆电阻切换方法
公开(公告)号：EP1507297A3
公开(公告)日：2006-04-26
申请号：EP04013726.7
申请日：2004-06-11
申请人： SHARP KABUSHIKI KAISHA
发明人： Zhuang, Wei-Wei , Li, Tingkai , Evans, David Russell , Hsu, Sheng Teng , Pan, Wei
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes: depositing by MOCVD, a seed layer of PCMO thin film, in highly crystalline form, having a thickness of between about 50Å to 300Å, depositing a second PCMO thin film layer on the seed layer by spin coating, having a thickness of between about 500Å to 3000Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about -4V to -5V, having a pulse width of between about 75 nsec to 1 µsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 µsec,

7. 发明公开

EP1403920A3 Method of fabricating self-aligned cross-point memory array 有权
标题翻译： Herstellungsverfahrenfüreine selbstausgerichtete Kreuzpunkt-Speichermatrix
公开(公告)号：EP1403920A3
公开(公告)日：2006-01-25
申请号：EP03254924.8
申请日：2003-08-07
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei
IPC分类号： H01L21/8246 , H01L27/10
CPC分类号： H01L27/24 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101
摘要： A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N + region; implanting ions to form a shallow P + region on the N + region to form a P + /N junction; depositing a barrier metal layer on the P + region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P + region and the N + region to forma trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer; patterning and etching the top electrode layer; and completing the memory array structure.
摘要翻译：通过沉积与底部电极自对准的孤立的钙钛矿金属氧化物电池柱（24）来制造自对准交叉点存储器阵列。自对准交叉点存储器阵列的制造包括：（a）在包括支撑电子结构的衬底上形成p阱区域（11）; （b）注入离子以形成深N +>区域（12）; （c）在N +>区域上注入离子以形成浅P +>区以形成P +> / N结; （d）在P +>区域（14）上沉积阻挡金属（16）层; （e）在阻挡层上沉积底部电极层; （f）在底层上沉积牺牲层; （g）图案化和蚀刻该结构以去除牺牲层，底层，势垒层，P +>区域和N +>部分的部分以形成沟槽; （h）沉积氧化物（22）以填充沟槽; （i）图案化和蚀刻牺牲层; （j）沉积与剩下的底部电极层自对准的钙钛矿金属氧化物层; （k）沉积顶部电极层（30）; （l）图案化和蚀刻顶部电极层; 和（m）完成存储器阵列结构。

8. 发明公开

EP1463060A3 Method of fabricating nano-scale resistance cross-point memory array and device 有权转让
标题翻译：一种用于在纳米范围内和装置产生的电阻的交叉点存储器的过程
公开(公告)号：EP1463060A3
公开(公告)日：2005-06-15
申请号：EP04251472.9
申请日：2004-03-15
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Zhuang, Weiwei , Pan, Wei , Zhang, Fengyan
IPC分类号： G11C11/16 , G11C11/22 , H01L27/115 , H01L27/22
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate (60); depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer (78) in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate (60); a first connection line (76) formed on the substrate; a colossal magnetoresistive layer (78) formed on the first connection line; a silicon nitride layer (82) formed on a portion of the colossal magnetoresistive layer; and a second connection line formed (86) adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

9. 发明公开

EP1507297A2 Method for obtaining reversible resistance switches in a PCMO thin film deposited on a highly crystallized seed layer 有权
标题翻译：一种用于在沉积在高度结晶种子层上的PCMO薄膜的可逆电阻切换方法
公开(公告)号：EP1507297A2
公开(公告)日：2005-02-16
申请号：EP04013726.7
申请日：2004-06-11
申请人： Sharp Kabushiki Kaisha
发明人： Zhuang, Wei-Wei , Li, Tingkai , Evans, David Russell , Hsu, Sheng Teng , Pan, Wei
IPC分类号： H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes: depositing by MOCVD, a seed layer of PCMO thin film, in highly crystalline form, having a thickness of between about 50Å to 300Å, depositing a second PCMO thin film layer on the seed layer by spin coating, having a thickness of between about 500Å to 3000Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about -4V to -5V, having a pulse width of between about 75 nsec to 1 µsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 µsec,
摘要翻译：一种用于获得可逆电阻法在PCMO薄膜开关当用高度结晶的晶种层集成包括：通过MOCVD，PCMO薄膜的种子层沉积，在高结晶形式，其具有的厚度为约50埃之间，以300埃，沉积通过旋涂法在籽晶层上的第二PCMO薄膜层，其厚度在约500埃到3000埃的，以形成组合的PCMO层; 通过施加介于约-4 V至-5V的负的电脉冲，其具有介于约75纳秒的脉冲宽度为1 .mu.sec增加组合PCMO膜在半导体器件的电阻; 并且通过施加约+ 2.5V到一个正的电脉冲到+ 4V，具有脉冲减少在一个半导体器件中的合并的PCMO层的电阻宽度大于2.0微秒，

10. 发明公开

EP1403920A2 Method of fabricating self-aligned cross-point memory array 有权
标题翻译：一种制造自对准的交叉点存储器阵列的方法
公开(公告)号：EP1403920A2
公开(公告)日：2004-03-31
申请号：EP03254924.8
申请日：2003-08-07
申请人： SHARP KABUSHIKI KAISHA
发明人： Hsu, Sheng Teng , Pan, Wei , Zhuang, Weiwei
IPC分类号： H01L21/8246 , H01L27/10
CPC分类号： H01L27/24 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/101
摘要： A method of fabricating a self-aligned cross-point memory array includes preparing a substrate, including forming any supporting electronic structures; forming a p-well area on the substrate; implanting ions to form a deep N + region; implanting ions to form a shallow P + region on the N + region to form a P + /N junction; depositing a barrier metal layer on the P + region; depositing a bottom electrode layer on the barrier metal layer; depositing a sacrificial layer or silicon nitride layer on the bottom electrode layer; patterning and etching the structure to remove portions of the sacrificial layer, the bottom electrode layer, the barrier metal layer, the P + region and the N + region to forma trench; depositing oxide to fill the trench; patterning and etching the sacrificial layer; depositing a PCMO layer which is self-aligned with the remaining bottom electrode layer; depositing a top electrode layer; patterning and etching the top electrode layer; and completing the memory array structure.

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