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1. 发明公开

EP3247030A1 A VOLTAGE-REGULATOR CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD 有权
标题翻译：电压调节器电路，相应的电子装置和方法
公开(公告)号：EP3247030A1
公开(公告)日：2017-11-22
申请号：EP16204318.6
申请日：2016-12-15
申请人： STMicroelectronics S.r.l.
发明人： BURGIO, Carmelo , GIACOMINI, Mauro
IPC分类号： H02M3/158 , G05F1/10 , G05F1/56 , H02M3/335 , H02M1/00
CPC分类号： G05F1/575 , G05F1/10 , G05F1/56 , H02M3/1584 , H02M3/33515 , H02M2001/0045
摘要： A voltage-regulator circuit with a current-adder output node (106) for supplying a load (L) with a load current (I load ) at a regulated output voltage (V load ) includes:
- an analog portion (102) sensitive to the output voltage (V load ) and including one or more reference-voltage sources (V ref N), the analog portion (102) applying to the current-adder node (106) a first current (I analog ) that is a function of the difference between the output voltage (V load ) and the reference voltage (V ref N) ; and
- a digital portion (104) including an integrator (I' analog ) sensitive to the first current (I analog ).
The integrator is coupled to a current source for applying to the current-adder node (106) a second current (I digital ), so that the first current (I analog ) and the second current (I digital ) supply on the current-adder output (106) a load current (I load ) at the aforesaid regulated output voltage (V load ).
摘要翻译：一种具有电流加法器输出节点（106）的电压调节器电路，用于以调节的输出电压（Vload）向负载（L）供应负载电流（Iload），所述电压调节器电路包括： - 模拟部分（102）电压（Vload）并且包括一个或多个参考电压源（VrefN），模拟部分（102）向电流加法器节点（106）施加作为输出电压之间的差的函数的第一电流（Ianalog）（Vload）和参考电压（VrefN）; 和 - 包括对第一电流（Ianalog）敏感的积分器（Ianalog）的数字部分（104）。积分器耦合到电流源，用于向电流加法器节点（106）施加第二电流（Idigital），使得电流加法器输出（106）上的第一电流（Ianalog）和第二电流（Idigital））在上述调节的输出电压（Vload）下的负载电流（Iload）。

2. 发明公开

EP4191647A1 CRACK DETECTOR FOR SEMICONDUCTOR DIES 审中-实审
公开(公告)号：EP4191647A1
公开(公告)日：2023-06-07
申请号：EP22207185.4
申请日：2022-11-14
申请人： STMicroelectronics S.r.l. , STMicroelectronics International N.V.
发明人： GIACOMINI, Mauro , DISEGNI, Fabio Enrico Carlo , NARWAL, Rajesh , SAINI, Pravesh Kumar , HARESHBHAI NIRANJANI, Mayankkumar
IPC分类号： H01L21/66 , H01L23/58
摘要： An assembly for detecting a structural defect in a semiconductor die (30), comprising a defect-detection sensor and computing means (43), wherein the defect-detection sensor includes: a plurality of resistive paths (38a-d) of electrical-conductive material in the semiconductor die (30), each of which has a first end (39') and a second end (39") and extends proximate a perimeter (32a) of the semiconductor die; and a plurality of signal-generation structures (40a-40d, 45), each coupled to a respective resistive path (38a-d) and configured to supply a test signal to the resistive path (38a-d). The computing means are configured to: control the signal-generation structures to generate the test signals; acquire the test signals in each resistive paths (38a-d); test an electrical feature of the resistive paths (38a-d) by performing an analysis of the test signals acquired; and detect the presence of the structural defect in the semiconductor die (30) based on a result of the analysis of the test signals acquired.

3. 发明公开

EP3026818A1 METHOD OF CALIBRATING A SAR A/D CONVERTER AND SAR-A/D CONVERTER IMPLEMENTING SAID METHOD 有权转让
标题翻译：方法用于校准SAR模拟/数字转换器和SAR模拟/数字转换器用于所述方法的实现
公开(公告)号：EP3026818A1
公开(公告)日：2016-06-01
申请号：EP15189321.1
申请日：2015-10-12
申请人： STMicroelectronics S.r.l.
发明人： BURGIO, Carmelo , GIACOMINI, Mauro
IPC分类号： H03M1/10 , H03M1/46
CPC分类号： H03M1/1047 , H03M1/00 , H03M1/0695 , H03M1/1033 , H03M1/12 , H03M1/1245 , H03M1/462 , H03M1/466 , H03M1/687 , H03M1/802 , H03M1/804 , H03M1/806 , H03M1/808
摘要： The present disclosure relates to a method of self-calibration of a SAR-A/D converter, comprising a N bit -bit digital-to-analog converter (DAC) for outputting a N bit -bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C MSB ) having a plurality N Th of thermometer elements T j (1) and a second subconverter (C LSB ) having a plurality of binary-weighted elements N Bin , said output code being defined by a thermometer scale S Th having a number of levels equal to 2 NBitTh +1. The method is characterized in that it comprises the steps of:
- measuring, for each thermometer element of said plurality N Th of thermometer elements T j , an error value;
- determining a mean value (µ) of these values;
- dividing said plurality N Th of thermometer elements T j into a first subset (X) and a second subset (Y) each containing an identical number of values (x, y), equal to N Th /2, wherein said first subset (X) comprises the thermometer elements T j whose values are closer to said mean value (µ) as long as the error of the sum of thermometer elements T j of the first subset (X) is not worse than the error value of the element farthest from said mean value (µ) of said first subset (X) and said second subset (Y) comprising all the remaining thermometer elements T j ;
- generating said thermometer scale, on the assumption that:
- each level m i of said thermometer scale S Th , with i ranging from 0 to N Th /2, will be the incremental sum of each value (x) of said first ordered subset X;
- each further level m i of said thermometer scale S Th , with i ranging from N Th /2+1 to N Th , will be the sum of all the values (y) of said second subset Y plus the incremental sum of the elements (x) of the subset X in any order;
- generating said output code (OUTPUT) according to said thermometer scale S Th .
摘要翻译：本发明涉及一种SAR A / D转换器的自校准的方法，包括一个n位的位的数字 - 模拟转换器（DAC），用于输出一个廷n比特位输出代码，所述数字到模拟转换器（DAC），包括第一子转换器具有具有二进制加权元件的多元性温度计元件T J（1）的N个Th和第二子转换器（C LSB）（C MSB）N滨所述输出代码被定义通过温度计比例S的Th具有多个相等的水平，以2 NBitTh 1。该方法的特征在于，这样做是包括以下步骤： - 测量，为温度计元件T J，误差值的温度计，所述多个第N中的每个元件; - 确定性采矿平均值合成值（μ）; - 将温度计元件T j的所述多个n个成第一个子集（X）和第二子集（Y）各以等于第N / 2个值的数目相同（X，Y）含有worin所述第一子组（ X）包括温度计元件T J，其值更接近所述平均值（μ），只要所述第一子集（X）的温度计元件T j的总和的误差不大于所述元件最远的误差值差从所述平均值所述第一子组（X）和（μ）所述第二子组（Y），其包括所有剩余的温度计元件T J; - 产生所述温度计的规模，这样的假设： - 每个级别。所述温度计比例S的Th的MI，i的范围从0到N的Th / 2，将说第一有序子集X的每个值（X）的所述增量总和 ; - 说温度计比例S的Th的每此外水平MI，i的范围从第N / 2 + 1至第N，将所述第二子组Y加上元素的增量之和的所有值（Y）的总和（ x）的任何顺序的子集x的; - 所述产生雅丁到所述温度计比例S个输出码（OUTPUT）。

4. 发明授权

EP3247030B1 A VOLTAGE-REGULATOR CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD 有权
公开(公告)号：EP3247030B1
公开(公告)日：2019-02-13
申请号：EP16204318.6
申请日：2016-12-15
申请人： STMicroelectronics S.r.l.
发明人： BURGIO, Carmelo , GIACOMINI, Mauro
IPC分类号： H02M3/158 , G05F1/10 , G05F1/56 , H02M3/335 , H02M1/00

5. 发明授权

EP3026818B1 METHOD OF SELF-CALIBRATING A SAR A/D CONVERTER AND SAR-A/D CONVERTER IMPLEMENTING SAID METHOD 有权转让
标题翻译：自校准SAR A / D转换器和SAR-A / D转换器的方法实现所述方法
公开(公告)号：EP3026818B1
公开(公告)日：2018-03-28
申请号：EP15189321.1
申请日：2015-10-12
申请人： STMicroelectronics S.r.l.
发明人： BURGIO, Carmelo , GIACOMINI, Mauro
IPC分类号： H03M1/10 , H03M1/46 , H03M1/68 , H03M1/80
CPC分类号： H03M1/1047 , H03M1/00 , H03M1/0695 , H03M1/1033 , H03M1/12 , H03M1/1245 , H03M1/462 , H03M1/466 , H03M1/687 , H03M1/802 , H03M1/804 , H03M1/806 , H03M1/808
摘要： The present disclosure relates to a method of self-calibration of a SAR-A/D converter, comprising a N bit -bit digital-to-analog converter (DAC) for outputting a N bit -bit output code, said digital-to-analog converter (DAC) comprising a first subconverter (C MSB ) having a plurality N Th of thermometer elements T j (1) and a second subconverter (C LSB ) having a plurality of binary-weighted elements N Bin , said output code being defined by a thermometer scale S Th having a number of levels equal to 2 NBitTh +1. The method is characterized in that it comprises the steps of: - measuring, for each thermometer element of said plurality N Th of thermometer elements T j , an error value; - determining a mean value (µ) of these values; - dividing said plurality N Th of thermometer elements T j into a first subset (X) and a second subset (Y) each containing an identical number of values (x, y), equal to N Th /2, wherein said first subset (X) comprises the thermometer elements T j whose values are closer to said mean value (µ) as long as the error of the sum of thermometer elements T j of the first subset (X) is not worse than the error value of the element farthest from said mean value (µ) of said first subset (X) and said second subset (Y) comprising all the remaining thermometer elements T j ; - generating said thermometer scale, on the assumption that: - each level m i of said thermometer scale S Th , with i ranging from 0 to N Th /2, will be the incremental sum of each value (x) of said first ordered subset X; - each further level m i of said thermometer scale S Th , with i ranging from N Th /2+1 to N Th , will be the sum of all the values (y) of said second subset Y plus the incremental sum of the elements (x) of the subset X in any order; - generating said output code (OUTPUT) according to said thermometer scale S Th .

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