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1. 发明公开

EP1361603A3 Method for manufacturing electronic circuits integrated on a semiconductor substrate 审中-公开
标题翻译：一种用于在半导体衬底上的集成电路的生产过程
公开(公告)号：EP1361603A3
公开(公告)日：2004-04-14
申请号：EP03009600.2
申请日：2003-04-29
申请人： STMicroelectronics S.r.l.
发明人： Alba, Simone , Ciovacco, Francesco , Colombo, Roberto , Savardi, Chiara
IPC分类号： H01L21/3065 , H01L21/768 , H01L21/311 , H01L21/3213 , H01L21/027
CPC分类号： H01L21/823437 , H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31138 , H01L21/31144 , H01L21/32139 , H01L21/76804 , H01L21/76816
摘要： A method for manufacturing semiconductor-integrated electronic circuits (CI) comprising the steps of: depositing an auxiliary layer (30) on a substrate (20); depositing a layer (40) of screening material on the auxiliary layer (30); selectively removing the layer (40) of screening material to provide a first opening (41) in the layer (40) of screening material and expose an area of the auxiliary layer (30); and removing this area of the auxiliary layer (30) to form a second opening (31) in the auxiliary layer (30), whose cross-section narrows toward the substrate (20) to expose an area of the substrate (20) being smaller than the area exposed by the first opening (41).

2. 发明授权

EP1582922B1 Nonlithographic method of defining geometries for plasma and/or ion implantation treatments on a semiconductor wafer 有权
标题翻译：定义非光刻工艺来图案化区域的半导体晶片的血浆和/或离子注入处理
公开(公告)号：EP1582922B1
公开(公告)日：2008-11-26
申请号：EP04425243.5
申请日：2004-04-01
申请人： STMicroelectronics S.r.l.
发明人： Alba, Simone , Romeo, Carmelo
IPC分类号： G03F1/16
CPC分类号： G03F7/0015 , G03F1/20 , H01J2237/0453 , H01J2237/31788

3. 发明公开

EP1850369A1 Manufacturing process of an organic mask for microelectronic industry 审中-公开
标题翻译： Verfahren zur Herstellung einer organischen Maskefürdie Mikroelektronikindustrie
公开(公告)号：EP1850369A1
公开(公告)日：2007-10-31
申请号：EP06425283.6
申请日：2006-04-28
申请人： STMicroelectronics S.r.l.
发明人： Piumi, Daniele , Capetti, Gianfranco , Alba, Simone , Demuro, Carlo , De Simone, Danilo
IPC分类号： H01L21/027 , H01L21/033 , H01L21/308
CPC分类号： H01L21/0271 , H01L21/0332 , H01L21/0338 , H01L21/3081 , H01L21/3088
摘要： A process for manufacturing an organic mask for the microelectronics industry, including the steps of: forming an organic layer (3) on a substrate (2); forming an inorganic mask (6a) on the organic layer (3); and etching selectively the organic layer (3) through the inorganic mask (6a). Furthermore, the step of forming the inorganic mask (6a) envisages: forming at least a first auxiliary layer (5) of a first inorganic material on the organic layer (3); forming a mask layer (6) of a second inorganic material different from the first inorganic material on the first auxiliary layer (5); and shaping the mask layer (6) by means of a dual-exposure lithographic process.
摘要翻译：一种制造用于微电子工业的有机掩模的方法，包括以下步骤：在衬底（2）上形成有机层（3）; 在有机层（3）上形成无机掩模（6a）; 并通过无机掩模（6a）选择性地蚀刻有机层（3）。此外，形成无机掩模（6a）的步骤设想：在有机层（3）上至少形成第一无机材料的第一辅助层（5）; 在所述第一辅助层（5）上形成与所述第一无机材料不同的第二无机材料的掩模层（6）; 以及通过双曝光光刻工艺成形掩模层（6）。

4. 发明公开

EP1582922A1 Nonlithographic method of defining geometries for plasma and/or ion implantation treatments on a semiconductor wafer 有权
标题翻译：定义非光刻工艺来图案化区域的半导体晶片的血浆和/或离子注入处理
公开(公告)号：EP1582922A1
公开(公告)日：2005-10-05
申请号：EP04425243.5
申请日：2004-04-01
申请人： STMicroelectronics S.r.l.
发明人： Alba, Simone , Romeo, Carmelo
IPC分类号： G03F1/16
CPC分类号： G03F7/0015 , G03F1/20 , H01J2237/0453 , H01J2237/31788
摘要： A method of successfully defining (nanometric) geometries for plasma and/or ion implantation treatments of a semiconductor wafer has been found that is decisively more cost effective than the previously known approaches.
A reusable laminar mask of a material that is mechanically selfsustaining, lithographically definable and dry etchable is fabricated by lithographically defining on a mechanically selfsustaining laminar substrate of a dry etchable material the desired geometries and subsequently dry etching it to produce the desired apertures through the whole thickness of the substrate. After removing the resist mask used for lithographically defining and etching the apertures through the laminar substrate, a layer of a refractory material having a substantial resistance to plasmas is deposited over the surface of the defined and etched laminar substrate that will eventually face toward the plasma or the ion source.
The so fabricated mask (or mask electrode) is placed in contact or at a relatively small distance that may be comprised between 1 and 5 millimeters, from the surface of an ordinarily supported wafer to be processed and if the mask is held spaced from the surface of the wafer it is preferably coupled to an RF power source.
Most preferably, the laminar substrate should be electrically conductive because, according to preferred embodiments of this invention, the reusable mask is fed with RF power during use.
It has been found that it is possible to achieve an outstandingly higher productivity and a decisive cost abatement by avoiding the need of lithographically defining the required geometries on the semiconductor wafer as well as of defining the geometries by direct writing on a resist layer with a focused electron beam (electron brush).

5. 发明公开

EP1361603A2 Method for manufacturing electronic circuits integrated on a semiconductor substrate 审中-公开
标题翻译：一种用于在半导体衬底上的集成电路的生产过程
公开(公告)号：EP1361603A2
公开(公告)日：2003-11-12
申请号：EP03009600.2
申请日：2003-04-29
申请人： STMicroelectronics S.r.l.
发明人： Alba, Simone , Ciovacco, Francesco , Colombo, Roberto , Savardi, Chiara
IPC分类号： H01L21/3065
CPC分类号： H01L21/823437 , H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/3081 , H01L21/3086 , H01L21/3088 , H01L21/31138 , H01L21/31144 , H01L21/32139 , H01L21/76804 , H01L21/76816
摘要： A method for manufacturing semiconductor-integrated electronic circuits (CI) comprising the steps of:

depositing an auxiliary layer (30) on a substrate (20);
depositing a layer (40) of screening material on the auxiliary layer (30);
selectively removing the layer (40) of screening material to provide a first opening (41) in the layer (40) of screening material and expose an area of the auxiliary layer (30); and
removing this area of the auxiliary layer (30) to form a second opening (31) in the auxiliary layer (30), whose cross-section narrows toward the substrate (20) to expose an area of the substrate (20) being smaller than the area exposed by the first opening (41).
摘要翻译：一种用于制造半导体集成电子电路（CI）包括以下步骤的方法：在一个基板的辅助层（30）（20）上沉积; 该辅助层上沉积屏蔽材料的层（40）（30）; 选择性地去除屏蔽材料的层（40），以提供在屏蔽材料的层（40）的第一开口（41）和暴露于（30）的辅助层的区域; 和除去所述辅助层（30）的该区域，以形成在辅助层（30），其横截面朝着基板（20）变窄在（20）的基板的区域，以露出的第二开口（31）小比由所述第一开口（41）的曝光区域。

6. 发明公开

EP1394835A1 A method and apparatus for detecting a leak of external air into a plasma reactor 审中-公开
标题翻译：一种用于在等离子体反应器中通过泄漏检测Aussenlufteindringung方法和装置
公开(公告)号：EP1394835A1
公开(公告)日：2004-03-03
申请号：EP02425536.6
申请日：2002-08-29
申请人： STMicroelectronics S.r.l.
发明人： Ciovacco, Francesco , Somboli, Fabio , Fazio, Giuseppe , Alba, Simone
IPC分类号： H01J37/32
CPC分类号： H01J37/3244
摘要： A method (300) and a corresponding apparatus for detecting a leak of external air into a plasma reactor are proposed. The method of the invention includes the steps of: establishing (340) a plasma inside the reactor, the plasma having a composition suitable to generate at least one predetermined compound when reacting with the air, detecting (345) a light emission of the plasma, and analyzing (350-375) the light emission to identify the presence of the at least one predetermined compound.
摘要翻译：的方法（300），以及用于检测外部空气的漏入等离子体反应器中的相应设备的提议。本发明的方法包括以下步骤：建立（340）一个反应器内的等离子体中，具有适合于产生至少一个预定的化合物当与空气反应生成的组合物的等离子体，检测（345）的等离子体的发光，和分析（350-375）的光发射以识别至少一个预定的化合物的存在。

7. 发明授权

EP0848428B1 Method for assessing the effects of plasma treatments on wafers of semicondutor material 失效
标题翻译：的方法来确定的等离子体处理在半导体晶片上的影响
公开(公告)号：EP0848428B1
公开(公告)日：2003-04-23
申请号：EP96830625.8
申请日：1996-12-16
申请人： STMicroelectronics S.r.l.
发明人： Ghio, Emilio , Alba, Simone , Colognese, Andrea , Maugain, François , Rivera, Giovanni Via V. Alfieri, 8
IPC分类号： H01L29/00 , H01L21/66
CPC分类号： H01L22/20 , H01L22/12

8. 发明授权

EP0848422B1 Process for the manufacture of floating-gate non-volatile memories 失效
标题翻译：一种制备非易失性存储器单元具有浮栅过程
公开(公告)号：EP0848422B1
公开(公告)日：2002-03-27
申请号：EP96830624.1
申请日：1996-12-16
申请人： STMicroelectronics S.r.l.
发明人： Ghio, Emilio , Alba, Simone , Colognese, Andrea
IPC分类号： H01L21/8247 , H01L21/336
CPC分类号： H01L29/66825 , H01L21/28176

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