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1. 发明公开

EP1098366A1 Semiconductor connection structure and method 失效
标题翻译： Halbleiterverbindungsstruktur und Verfahren
公开(公告)号：EP1098366A1
公开(公告)日：2001-05-09
申请号：EP01100643.4
申请日：1995-12-05
申请人： STMicroelectronics, Inc.
发明人： Miller, Robert O. , Smith, Gregory C.
IPC分类号： H01L23/522 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76852 , H01L21/76865 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An electrical connection structure is provided for protecting a barrier metal layer within a contact opening during the formation of an aluminum interconnection layer overlying a tungsten plugged connection structure. The deposited tungsten plug overlying the barrier metal layer is etched back sufficiently to create a slight recess at the opening. A thin layer of tungsten is then selectively deposited for filling the recess. This layer acts as an etch stop during aluminum interconnection layer formation and protects the underlying barrier metal layer.
摘要翻译：提供一种电连接结构，用于在覆盖钨插入连接结构的铝互连层的形成期间保护接触开口内的阻挡金属层。覆盖阻挡金属层的沉积钨丝塞被充分回蚀，以在开口处产生轻微的凹陷。然后选择性地沉积薄层的钨以填充凹部。在铝互连层形成期间，该层用作蚀刻停止层并保护下面的阻挡金属层。

2. 发明授权

EP0973195B1 Silver metallization by damascene method 有权
标题翻译：银色金属镶嵌手段
公开(公告)号：EP0973195B1
公开(公告)日：2012-04-11
申请号：EP99304867.7
申请日：1999-06-22
申请人： STMicroelectronics, Inc.
发明人： Chan, Tsiu C. , Chiu, Anthony M. , Smith, Gregory C.
IPC分类号： H01L21/768 , H01L21/288 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76877 , H01L23/53242 , H01L23/53252 , H01L2221/1089 , H01L2924/0002 , H01L2924/00

3. 发明授权

EP0785573B1 Method of forming raised source/drain regions in an integrated circuit 失效
标题翻译：的集成电路中形成凸起的源区和漏区的方法
公开(公告)号：EP0785573B1
公开(公告)日：2005-12-14
申请号：EP97200810.6
申请日：1995-10-27
申请人： STMicroelectronics, Inc.
发明人： Chan, Tsiu Chiu , Smith, Gregory C.
IPC分类号： H01L21/336 , H01L21/60
CPC分类号： H01L29/0847 , H01L29/41775 , H01L29/41783 , H01L29/6659 , H01L29/66628 , H01L29/7833
摘要： A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A transistor encapsulated in a dielectric is formed over a substrate. First source and drain regions are formed in the substrate adjacent the transistor. Metal raised second source and drain regions are formed which overly exposed portions of the first substrate source and drain regions adjacent the transistor. The raised second source and drain regions are formed such that an upper surface of the raised second source and drain regions are substantially planar with an upper surface of the transistor. The dielectric encapsulating the transistor electrically isolates the transistor from the raised second source and drain regions.

4. 发明授权

EP1732113B1 Silver metallization by damascene method 有权
标题翻译：银色金属镶嵌由
公开(公告)号：EP1732113B1
公开(公告)日：2012-10-10
申请号：EP06076564.1
申请日：1999-06-22
申请人： STMicroelectronics, Inc.
发明人： Chan, Tsiu C. , Chiu, Anthony M. , Smith, Gregory C.
IPC分类号： H01L21/288 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76877 , H01L23/53242 , H01L23/53252 , H01L2221/1089 , H01L2924/0002 , H01L2924/00

5. 发明公开

EP1732113A3 Silver metallization by damascene method 有权
标题翻译：银色金属镶嵌由
公开(公告)号：EP1732113A3
公开(公告)日：2011-08-31
申请号：EP06076564.1
申请日：1999-06-22
申请人： STMicroelectronics, Inc.
发明人： Chan, Tsiu C. , Chiu, Anthony M. , Smith, Gregory C.
IPC分类号： H01L21/288 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76877 , H01L23/53242 , H01L23/53252 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of forming interconnects in an integrated circuit, comprising: forming a dielectric layer over a substrate; forming a groove (114) for an interconnect in the dielectric layer; forming an aluminium seed layer over the upper surface of the dielectric layer, over sidewalls of the groove, and over a bottom of the groove to a thickness of approximately 200 Å; zincating the substrate to form a zinc coating on the aluminium seed layer; plating the substrate with silver to form a conformal silver layer (116) on an upper surface of the dielectric layer and on sidewalls of the groove, filling an unfilled portion of the groove; and removing portions of the conformal silver layer on the dielectric layer, leaving a silver interconnect within the groove.

6. 发明授权

EP0720228B1 Method of making a semiconductor connection structure 失效
标题翻译：一种生产化合物半导体结构的方法
公开(公告)号：EP0720228B1
公开(公告)日：2002-07-10
申请号：EP95308801.0
申请日：1995-12-05
申请人： STMicroelectronics, Inc.
发明人： Miller, Robert O. , Smith, Gregory C.
IPC分类号： H01L23/522 , H01L23/532
CPC分类号： H01L21/76843 , H01L21/76849 , H01L21/76852 , H01L21/76865 , H01L21/76877 , H01L21/76879 , H01L23/5226 , H01L23/53223 , H01L2924/0002 , H01L2924/00

7. 发明公开

EP1732113A2 Silver metallization by damascene method 有权
标题翻译： Silbermetallisierung durch Damaszenverfahren
公开(公告)号：EP1732113A2
公开(公告)日：2006-12-13
申请号：EP06076564.1
申请日：1999-06-22
申请人： STMicroelectronics, Inc.
发明人： Chan, Tsiu C. , Chiu, Anthony M. , Smith, Gregory C.
IPC分类号： H01L21/288 , H01L21/768 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76877 , H01L23/53242 , H01L23/53252 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method of forming interconnects in an integrated circuit, comprising: forming a dielectric layer over a substrate; forming a groove for an interconnect in the dielectric layer; forming an aluminium seed layer over the upper surface of the dielectric layer, over sidewalls of the groove, and over a bottom of the groove to a thickness of approximately 200 Å; zincating the substrate to form a zinc coating on the aluminium seed layer; plating the substrate with silver to form a conformal silver layer on an upper surface of the dielectric layer and on sidewalls of the groove, filling an unfilled portion of the groove; and removing portions of the conformal silver layer on the dielectric layer, leaving a silver interconnect within the groove.
摘要翻译：一种在集成电路中形成互连的方法，包括：在衬底上形成电介质层; 在所述电介质层中形成用于互连的凹槽（114）; 在所述电介质层的上表面上方，在所述凹槽的侧壁上方，并在所述凹槽的底部上方形成厚度约为的铝种子层; 对基材进行锌化以在铝籽晶层上形成锌涂层; 用银镀覆衬底以在电介质层的上表面和槽的侧壁上形成共形银层（116），填充凹槽的未填充部分; 并且去除介电层上的共形银层的部分，在槽内留下银互连。

8. 发明授权

EP0720227B1 Electrical connection structure on an integrated circuit device comprising a plug with an enlarged head 失效
标题翻译：电连接结构上的集成电路装置，其具有PEG具有一扩大的头部
公开(公告)号：EP0720227B1
公开(公告)日：2004-12-01
申请号：EP95308800.2
申请日：1995-12-05
申请人： STMicroelectronics, Inc.
发明人： Smith, Gregory C.
IPC分类号： H01L23/485 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76804 , H01L23/485 , H01L2924/0002 , Y10S438/97 , H01L2924/00

9. 发明公开

EP0973195A1 Silver metallization by damascene method 有权
标题翻译： Silbermetallisierung手套Damaszenverfahren
公开(公告)号：EP0973195A1
公开(公告)日：2000-01-19
申请号：EP99304867.7
申请日：1999-06-22
申请人： STMicroelectronics, Inc.
发明人： Chan, Tsiu C. , Chiu, Anthony M. , Smith, Gregory C.
IPC分类号： H01L21/768 , H01L21/288 , H01L23/532
CPC分类号： H01L21/76873 , H01L21/2885 , H01L21/76843 , H01L21/76877 , H01L23/53242 , H01L23/53252 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： Silver interconnects (118) are formed by etching deep grooves (114) into an insulating layer (112) over the contact regions, exposing portions of the contact regions and defining the interconnects. The grooves (114) are etched with a truncated V- or U-shape, wider at the top than at any other vertical location, and have a minimum width of 0.25 µm or less. An optional adhesion layer and a barrier layer are sputtered onto surfaces of the groove, including the sidewalls, followed by sputter deposition of a seed layer. Where aluminum is employed as the seed layer, a zincating process may then be optionally employed to promote adhesion of silver to the seed layer. The groove (114) is then filled with silver (116) by plating in a silver solution, or with silver and copper by plating in a copper solution followed by plating in a silver solution. The filled groove (114) which results does not exhibit voids ordinarily resulting from sputter deposition of metal into such narrow, deep grooves, although seams may be intermittently present in portions of the filled groove where metal plated from the opposing sidewalls did not fuse flawlessly at the point of convergence. Portions of the silver (116) and other layers above the insulating material (112) are then removed by chemical-mechanical polishing, leaving a silver interconnect (118) connected to the exposed portion of the contact region (110) and extending over adjacent insulating regions to another contact region or a bond pad. Silver interconnects (118) thus formed may have smaller cross-sections, and thus a greater density in a given area, than conventional metallic interconnects.
摘要翻译：通过在接触区域上将深槽（114）蚀刻成绝缘层（112）形成银互连（118），暴露接触区域的部分并限定互连。凹槽（114）被蚀刻成截顶的V形或U形，在顶部比在任何其它垂直位置处更宽，并且具有0.25μm或更小的最小宽度。将可选的粘合层和阻挡层溅射到包括侧壁的凹槽的表面上，然后溅射沉积种子层。当铝用作种子层时，可以任选地使用锌化工艺以促进银与种子层的粘附。然后通过在银溶液中镀银，或者通过在铜溶液中电镀银和铜，然后在银溶液中电镀，将银（116）填充到银（116）中。所形成的填充凹槽（114）通常不会由金属溅射沉积到这种狭窄的深沟槽中而产生空隙，尽管接缝可以间断地存在于填充凹槽的部分中，其中从相对的侧壁电镀的金属没有完美融合融合点。然后通过化学机械抛光去除银（116）和绝缘材料（112）上方的其它层的部分，留下连接到接触区域（110）的暴露部分并延伸到相邻绝缘体上的银互连（118）区域到另一个接触区域或接合焊盘。如此形成的银互连（118）可以具有比常规金属互连更小的横截面，并且因此在给定区域中具有更大的密度。

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