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1. 发明公开

EP0926708A3 Method and apparatus for processing semiconductor wafers 审中-公开
标题翻译： Verfahren und Vorrichtung zur Behandlung von Halbleiterscheiben
公开(公告)号：EP0926708A3
公开(公告)日：2003-08-20
申请号：EP98310683.2
申请日：1998-12-23
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Hoinkis, Mark , Restaino, Darryl
IPC分类号： H01L21/00
CPC分类号： H01L21/6831 , H02N13/00
摘要： Method and apparatus are provided for processing semiconductor wafers, and in particular for determining a warpage of a wafer (14) for providing a minimum clamping voltage to an electrostatic chuck (ESC) when the wafer is subsequently processed thereon. The apparatus includes an electrostatic chuck (12, 120) and a control arrangement (16, 18, 20). The electrostatic chuck includes a clamping surface (13, 130) for clamping a wafer thereto by a clamping force that is dependent on a clamping voltage applied to the electrostatic chuck. The control arrangement is used to detect an inherent warpage in the wafer prior to a processing of that wafer, and determine a minimum clamping voltage from the measured warpage that is to be applied to the electrostatic chuck during a subsequent processing of the wafer. The minimum clamping voltage has a value for each wafer that securely clamps the wafer to the clamping surface and avoids excessive warpage and backside abrasion of the wafer. The control arrangement includes a suitable wafer warpage measuring tool (20, 50, 52, 54) such as, for example, a capacitance warpage measuring tool (50, 52, 54) or a optical warpage measuring tool (20) that measures the inherent warpage of a wafer, and an electrostatic chuck software control (18). The electrostatic chuck software control uses the measured warpages to determine and store data of a minimum clamping voltages and an associated wafer identification for each wafer for use in subsequently processing each wafer.
摘要翻译：该装置包括具有夹紧表面的单个双极静电卡盘（12），该夹紧表面用于当晶片被处理时通过施加到卡盘上的钳位电压的力来夹紧到晶片（14）。控制装置（16,18,20）在晶片在卡盘上被处理之前测量晶片的固有翘曲。翘曲用于确定在晶片处理期间施加到卡盘的最小钳位电压。

2. 发明公开

EP0926708A2 Method and apparatus for processing semiconductor wafers 审中-公开
标题翻译：用于治疗的半导体晶片的方法和设备
公开(公告)号：EP0926708A2
公开(公告)日：1999-06-30
申请号：EP98310683.2
申请日：1998-12-23
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Hoinkis, Mark , Restaino, Darryl
IPC分类号： H01L21/00
CPC分类号： H01L21/6831 , H02N13/00
摘要： Method and apparatus are provided for processing semiconductor wafers, and in particular for determining a warpage of a wafer (14) for providing a minimum clamping voltage to an electrostatic chuck (ESC) when the wafer is subsequently processed thereon. The apparatus includes an electrostatic chuck (12, 120) and a control arrangement (16, 18, 20). The electrostatic chuck includes a clamping surface (13, 130) for clamping a wafer thereto by a clamping force that is dependent on a clamping voltage applied to the electrostatic chuck. The control arrangement is used to detect an inherent warpage in the wafer prior to a processing of that wafer, and determine a minimum clamping voltage from the measured warpage that is to be applied to the electrostatic chuck during a subsequent processing of the wafer. The minimum clamping voltage has a value for each wafer that securely clamps the wafer to the clamping surface and avoids excessive warpage and backside abrasion of the wafer. The control arrangement includes a suitable wafer warpage measuring tool (20, 50, 52, 54) such as, for example, a capacitance warpage measuring tool (50, 52, 54) or a optical warpage measuring tool (20) that measures the inherent warpage of a wafer, and an electrostatic chuck software control (18). The electrostatic chuck software control uses the measured warpages to determine and store data of a minimum clamping voltages and an associated wafer identification for each wafer for use in subsequently processing each wafer.

3. 发明公开

EP0949673A3 Damascene structure comprising surrounding liner 审中-公开
标题翻译：镶嵌结构包括周围衬垫
公开(公告)号：EP0949673A3
公开(公告)日：2002-02-20
申请号：EP99302558.4
申请日：1999-03-31
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Clevenger, Lawrence A. , Filippi, Ronald G. , Hoinkis, Mark , Hurd, Jeffery L. , Iggulden, Roy C. , Palm, Herbert , Poetzlberger, Hans W. , Rodbell, Kenneth P. , Schnabel, Florian , Weber, Stefan , Mehter, Ebrahim A.
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76849 , H01L21/76876 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.

4. 发明公开

EP0949673A2 Damascene structure comprising surrounding liner 审中-公开
标题翻译： Damascenestruktur mit umgebenden Auskleidung
公开(公告)号：EP0949673A2
公开(公告)日：1999-10-13
申请号：EP99302558.4
申请日：1999-03-31
申请人： SIEMENS AKTIENGESELLSCHAFT , International Business Machines Corporation
发明人： Clevenger, Lawrence A. , Filippi, Ronald G. , Hoinkis, Mark , Hurd, Jeffery L. , Iggulden, Roy C. , Palm, Herbert , Poetzlberger, Hans W. , Rodbell, Kenneth P. , Schnabel, Florian , Weber, Stefan , Mehter, Ebrahim A.
IPC分类号： H01L21/768
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76849 , H01L21/76876 , H01L23/485 , H01L23/53223 , H01L2924/0002 , H01L2924/00
摘要： An conductor for interconnecting integrated circuit components having improved reliability. The conductor includes a liner surrounding at least three surfaces of the conductor, producing a low textured conductor. It has been found that low textured conductor results in improved electromigration lifetime.
摘要翻译：用于互连具有改进的可靠性的集成电路部件的导体。导体包括围绕导体的至少三个表面的衬垫，产生低纹理导体。已经发现，低纹理导体导致改善的电迁移寿命。

5. 发明公开

EP1022352A3 Method for forming metal interconnects with increased electromigration lifetime 审中-公开
标题翻译：一种用于生产金属的化合物具有增加的电迁移寿命过程
公开(公告)号：EP1022352A3
公开(公告)日：2002-01-02
申请号：EP99125723.9
申请日：1999-12-23
申请人： Infineon Technologies North America Corp. , International Business Machines Corporation
发明人： Schnabel, Rainer Florian , Hoinkis, Mark , Iggulden, Roy , Clevenger, Lawrence , Filippi, Ronald , Weber, Stefan , Weigand, Peter
IPC分类号： C23C14/32 , H01L21/3205 , H01L21/768 , H01L21/285
CPC分类号： H01L21/76864 , H01L21/2855 , H01L21/76841
摘要： A reliable interconnect for semiconductor integrated circuits is provided. The interconnect comprises a conductor and a liner formed thereunder by an ionized metal plasma physical vapor deposition process. The liner reduces the angular distribution as well as reducing the size of the grains in the conductor, which results in an increase in electromigration lifetime.

6. 发明公开

EP1032039A2 Vertical fuse and method of fabrication 有权
标题翻译： Vertikale Sicherung und deren Herstellungsverfahren
公开(公告)号：EP1032039A2
公开(公告)日：2000-08-30
申请号：EP00102357.1
申请日：2000-02-04
申请人： Infineon Technologies Corporation , International Business Machines Corporation
发明人： Weber, Stefan J. , Iggulden, Roy , Narayan, Chandrasekhar , Brintzinger, Axel Christoph , Hoinkis, Mark , van den Berg, Robert
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
摘要翻译：根据本发明的用于半导体器件的熔丝包括具有设置在其表面上的导电路径的基板，设置在基板上的电介质层和垂直于通过介电层垂直于表面设置并连接到导电路径的垂直熔丝垂直熔丝形成具有沿着空腔的垂直表面设置的衬垫材料的空腔，垂直表面被熔化以熔断熔丝。还包括制造垂直保险丝的方法。

7. 发明公开

EP1032039A3 Vertical fuse and method of fabrication 有权
标题翻译：垂直保险丝和制造方法
公开(公告)号：EP1032039A3
公开(公告)日：2000-12-20
申请号：EP00102357.1
申请日：2000-02-04
申请人： Infineon Technologies Corporation , International Business Machines Corporation
发明人： Weber, Stefan J. , Iggulden, Roy , Narayan, Chandrasekhar , Brintzinger, Axel Christoph , Hoinkis, Mark , van den Berg, Robert
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse for semiconductor devices in accordance with the present invention includes a substrate having a conductive path disposed on a surface thereof, a dielectric layer disposed on the substrate and a vertical fuse disposed perpendicularly to the surface through the dielectric layer and connecting to the conductive path, the vertical fuse forming a cavity having a liner material disposed along vertical surfaces of the cavity, the vertical surfaces being melted to blow the fuse. Methods for fabrication of the vertical fuse are also included.
摘要翻译：根据本发明的用于半导体器件的熔丝包括具有设置在其表面上的导电路径的衬底，设置在衬底上的电介质层以及垂直于电介质层的表面设置并垂直于导电路径连接的垂直熔丝垂直熔丝形成具有沿着空腔的垂直表面设置的衬里材料的空腔，所述垂直表面熔化以吹制熔丝。还包括制造垂直熔断器的方法。

8. 发明公开

EP1022352A2 Method for forming metal interconnects with increased electromigration lifetime 审中-公开
标题翻译： Verfahren zur Herstellung von Metallverbindungen miterhöhterElektromigrationslebensdauer
公开(公告)号：EP1022352A2
公开(公告)日：2000-07-26
申请号：EP99125723.9
申请日：1999-12-23
申请人： Infineon Technologies North America Corp. , International Business Machines Corporation
发明人： Schnabel, Rainer Florian , Hoinkis, Mark , Iggulden, Roy , Clevenger, Lawrence , Filippi, Ronald , Weber, Stefan , Weigand, Peter
IPC分类号： C23C14/32 , H01L21/3205 , H01L21/768 , H01L21/285
CPC分类号： H01L21/76864 , H01L21/2855 , H01L21/76841
摘要： A reliable interconnect for semiconductor integrated circuits is provided. The interconnect comprises a conductor and a liner formed thereunder by an ionized metal plasma physical vapor deposition process. The liner reduces the angular distribution as well as reducing the size of the grains in the conductor, which results in an increase in electromigration lifetime.
摘要翻译：提供了半导体集成电路的可靠互连。互连包括通过电离金属等离子体物理气相沉积工艺在其下形成的导体和衬垫。衬垫减小角分布以及减小导体中晶粒的尺寸，这导致电迁移寿命的增加。

9. 发明授权

EP1032039B1 Vertical fuse and method of fabrication 有权
标题翻译：垂直熔丝及其制备方法
公开(公告)号：EP1032039B1
公开(公告)日：2007-05-02
申请号：EP00102357.1
申请日：2000-02-04
申请人： Infineon Technologies AG , International Business Machines Corporation
发明人： Weber, Stefan J. , Iggulden, Roy , Narayan, Chandrasekhar , Brintzinger, Axel Christoph , Hoinkis, Mark , van den Berg, Robert
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00

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