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1. 发明授权

EP0426241B1 Process for the manufacture of a component to limit the programming voltage and to stabilise the voltage incorporated in an electric device with EEPROM memory cells 失效
标题翻译：一种用于在电子设备制备部件，用于限制所述编程电压和电压的稳定化具有EEPROM的存储单元的过程
公开(公告)号：EP0426241B1
公开(公告)日：1996-03-13
申请号：EP90202840.6
申请日：1990-10-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Cappelletti, Paolo , Corda, Giuseppe , Ghezzi, Paolo , Riva, Carlo , Vajana, Bruno
IPC分类号： H01L21/82 , H01L21/329 , H01L27/02 , G11C16/04
CPC分类号： H01L29/66106 , H01L27/115 , H01L27/11517 , Y10S148/174 , Y10S438/983

2. 发明公开

EP0451883A1 Process for the accomplishment of an ROM memory cell having a low drain capacity 失效
标题翻译： Verfahren zur Fertigung einer ROM-Speicherzelle mit einer niedrigenDrainkapazität。
公开(公告)号：EP0451883A1
公开(公告)日：1991-10-16
申请号：EP91200496.7
申请日：1991-03-07
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Cappelletti, Paolo , Vajana, Bruno , Lucherini, Silvia
IPC分类号： H01L27/112 , H01L21/82
CPC分类号： H01L27/11253 , H01L27/112 , H01L27/1126 , H01L27/11266
摘要： The process provides for the creation of regions of source (5) and drain (6) having different doping, wherein the doping, and thus the capacity, of the drain regions is lower than that of the drain regions.
摘要翻译：该过程提供了具有不同掺杂的源极（5）和漏极（6）的区域的产生，其中漏极区域的掺杂以及因此的漏极区域的电容低于漏极区域。

3. 发明公开

EP0426241A2 Process for the manufacture of a component to limit the programming voltage and to stabilise the voltage incorporated in an electric device with EEPROM memory cells 失效
标题翻译：一种制备组件，其用于限制所述编程电压和用于电压的与EEPROM存储单元的电组件中的稳定化工艺。
公开(公告)号：EP0426241A2
公开(公告)日：1991-05-08
申请号：EP90202840.6
申请日：1990-10-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Cappelletti, Paolo , Corda, Giuseppe , Ghezzi, Paolo , Riva, Carlo , Vajana, Bruno
IPC分类号： H01L21/82 , H01L21/329 , H01L27/02 , G11C16/04
CPC分类号： H01L29/66106 , H01L27/115 , H01L27/11517 , Y10S148/174 , Y10S438/983
摘要： The manufacturing process comprises a first step of formation of an N type sink (2) on a single-crystal silicon substrate (1), a second step of formation of an active area (14) on the surface of said sink (2), a third step of implantation of N- dopant in a surface region (4) of the sink (2) inside said active area (14), a fourth step of growth of a layer (5) of gate oxide over said region with N- dopant, a fifth step of N+ implantation (6; 9) inside said N- region, a sixth step of P+ implantation (7; 12) in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts (8, 18; 13, 23, 33) for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.
摘要翻译：制造过程包括形成N型水槽（2）中的在单结晶硅的第一步骤的底物（1）中，形成有源区（14）中的所述排水池的表面上的第二步骤（2） N-掺杂剂的植入在表面区域的第三步骤（4）所述有源区域内的水槽（2）（14），栅氧化物层（5）的生长在具有N-所述区域的第四步骤的掺杂剂，的N +注入的第五步骤（6; 9）在所述N-型区，P +注入（7; 12）的第六步骤在后期反弹位移位置相对于所述N +区域和形成外部触点中的第七步（8，18; 13，23，33），用于所述N +和P +区域。因此，存在所获得的齐纳二极管限幅器，具有一个截止电压的所有其是随时间稳定的，没有太大的依赖于温度，并且不要求另外的工艺步骤相对于那些通常有必要对EEPROM的存储单元的特征。

4. 发明公开

EP0730305A1 High voltage N-channel MOSFET in CMOS-type technology and relating manufacturing process 失效
标题翻译： CMOS技术和Herstellungsverfahren中的Hochspannungs-N-Kanal-MOSFET
公开(公告)号：EP0730305A1
公开(公告)日：1996-09-04
申请号：EP95830065.9
申请日：1995-02-28
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Vajana, Bruno , Baldi, Livio
IPC分类号： H01L29/00 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823878 , H01L27/0928
摘要： The present invention relates to a high-voltage N-channel MOS transistor manufactured with twin-well CMOS-type technology on a portion (6) of a semiconductor substrate (2) having a first type of conductivity.
This transistor comprises a source region (20,25) and drain region (20,25) having a second type of conductivity located respectively at the sides of a gate channel region (18).
摘要翻译：本发明涉及在具有第一类导电性的半导体衬底（2）的部分（6）上用双阱CMOS技术制造的高压N沟道MOS晶体管。该晶体管包括分别位于栅极沟道区域（18）的侧面处的具有第二类型导电性的源极区（20,25）和漏极区（20,25）。

5. 发明公开

EP0715312A1 Monolitically integrated generator of a plurality of voltage values 失效
标题翻译： Monolithischer integrierter发生器von verschiedenen Speisespannungswerten
公开(公告)号：EP0715312A1
公开(公告)日：1996-06-05
申请号：EP94830554.5
申请日：1994-11-30
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Pio, Frederico , Vajana, Bruno , Paruzzi, Paola
IPC分类号： G11C11/56 , G11C5/14
CPC分类号： G11C5/147 , G11C11/5621 , G11C16/30
摘要： The present invention relates to a monolithically integrable predetermined voltage generator (1) comprising a node (IN) held at a constant voltage (Vpp) and a plurality of circuit branches (2a, 2b, 2c and 2d) each of which incorporates at least one turn on control terminal (3a, 3b, 3c and 3d) and which are interconnected in such a manner that at least one of them leads to said node (IN). Across each of the branches (2a, 2b, 2c and 2d) a corresponding voltage drop is present when the branch is turned on and obtained from a certain number of active elements included in the branch. In accordance with a preferred embodiment, diode-connected MOS transistors are used as active elements. The generator also comprises an output terminal (OUT) associated with at least one of said branches at which is generated a predetermined voltage value.
A control signal is applied to at least one turn on control terminal (3a, 3b, 3c and 3d) of said plurality of branches for turning on a predetermined subset of said plurality of branches and generating at the output terminal (OUT) a voltage lower than that at said node (IN). Each of the predetermined voltage values is a predetermined combination of the voltage drops on the turned on branches.
In a preferred application, the generator of the present invention is used in a multilevel EEPROM memory circuit for generating a plurality of programming voltages for the memory cells.
摘要翻译：本发明涉及一种包括保持在恒定电压（Vpp）的节点（IN）和多个电路分支（2a，2b，2c和2d）的单片可积分预定电压发生器（1），每个电路分支包括至少一个打开控制终端（3a，3b，3c和3d），并以这样的方式相互连接，使得它们中的至少一个通向所述节点（IN）。在分支（2a，2b，2c和2d）中，当分支打开并从包括在分支中的一定数量的有源元件获得时，存在相应的电压降。根据优选实施例，二极管连接的MOS晶体管用作有源元件。发生器还包括与所述分支中的至少一个相关联的输出端子（OUT），在该输出端子产生预定电压值。控制信号被施加到所述多个分支的控制端子（3a，3b，3c和3d）上的至少一匝，用于导通所述多个分支的预定子集，并在输出端（OUT）处产生较低的电压比在所述节点（IN）处。预定电压值中的每一个都是开启分支上的电压降的预定组合。在优选的应用中，本发明的发生器用于产生用于存储单元的多个编程电压的多电平EEPROM存储器电路。

6. 发明公开

EP0714133A1 Twin-well manufacturing process for an EEPROM integrated device with reduced body effect 失效
标题翻译：对于具有低效应集成双阱EEPROM电路衬底制备方法
公开(公告)号：EP0714133A1
公开(公告)日：1996-05-29
申请号：EP94830544.6
申请日：1994-11-24
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Vajana, Bruno , Baldi, Livio
IPC分类号： H01L27/115 , H01L21/8247 , H01L27/105
CPC分类号： H01L27/11521 , H01L27/105 , H01L27/115 , H01L27/11558
摘要： A twin-well process for the manufacturing of an EEPROM integrated device comprises the steps of: selectively forming at least one first-conductivity-type well (7) in a first substrate portion (6) of a semiconductor substrate (1); forming in said first substrate portion (6) second-conductivity-type wells (10), outside said first-conductivity-type well (7); forming in said at least one first-conductivity-type well (7) and in said second-conductivity-type-wells (10) second-conductivity-type-channel MOSFETs and first-conductivity-type-channel MOSFETs, respectively, and simultaneously forming a plurality of EEPROM memory cells in a second substrate portion (5) in which no wells have been formed.
摘要翻译：为制造一个集成的EEPROM器件的双阱工艺包括下列步骤：有选择地形成至少一个第一导电型阱（7）在第一基片部（6）的半导体的衬底（1）; 在基底部分，所述第一成型（6）第二导电型的井（10），所述外部的第一导电型阱（7）; 形成在所述至少一个第一导电型阱（7）和在所述第二导电型阱（10）的第二导电型沟道MOSFET和第一导电型沟道MOSFET分别与同时在没有井已形成在第二基板部分（5）形成的EEPROM的存储单元的复数。

7. 发明公开

EP0613181A1 Bipolar transistor compatible with CMOS processes 失效
标题翻译： CMOS无源kompatibler双极晶体管。
公开(公告)号：EP0613181A1
公开(公告)日：1994-08-31
申请号：EP93830081.1
申请日：1993-02-26
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Vajana, Bruno , Ghio, Emilio
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L21/8249 , H01L21/8248 , H01L27/0623
摘要： A bipolar transistor (2), comprising a collector region (C1), base region (B1), and emitter region (E1), is a compatible type to CMOS processes leading to the formation, on a semiconductor substrate (10), of N-channel and P-channel MOS transistors having respective source and drain regions; in such transistor the collector region (C1) is a substrate diffused pocket (3) and the base region (B1) is formed within the diffused pocket (3) simultaneously with the source (8) and drain (9) regions of the P-channel MOS transistors (7). Further, the emitter region (E1) is incorporated, in turn, to the base region (B1) simultaneously with the source and drain regions of the N-channel MOS transistors.
摘要翻译：包括集电极区域（C1），基极区域（B1）和发射极区域（E1）的双极性晶体管（2）是与半导体衬底（10）上形成N沟道的CMOS工艺的兼容型 - 沟道和P沟道MOS晶体管，其具有各自的源极和漏极区域; 在这种晶体管中，集电极区域（C1）是衬底扩散袋（3），并且基底区域（B1）与扩散口袋（3）中的P-源极（8）和漏极（9）区域同时形成，通道MOS晶体管（7）。此外，发射极区域（E1）又与N沟道MOS晶体管的源极和漏极区域同时并入基极区域（B1）。

8. 发明公开

EP0450389A2 A low-capacitance, high breakdown voltage programmed cell structure for read-only memory circuits 失效
标题翻译：具有低电容和高击穿电压的泡孔结构编程的只读存储器电路。
公开(公告)号：EP0450389A2
公开(公告)日：1991-10-09
申请号：EP91104217.4
申请日：1991-03-19
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Ginami, Giancarlo , Laurin, Enrico , Lucherini, Silvia , Vajana, Bruno
IPC分类号： G11C17/12 , H01L27/112
CPC分类号： G11C17/12 , H01L27/112
摘要： A low-capacitance programmed cell structure (1) for read-only memory circuits comprises a field-effect transistor (2) having conventional source (5) and drain (6) regions separated by a channel region (9) overlaid by the gate (11) of the transistor (2). This structure (1) is completed by a so-called channel implant (12) only extending from the source region (5) for a predetermined distance.
摘要翻译：为只读存储器电路的低电容编程单元结构（1）包含（2），其具有（6）由一通道区域所分隔的区域（9）由栅极重叠的常规源（5）和漏区的场效应晶体管（晶体管11）（2）。该结构（1）由一个所谓的信道植入物（12）从源极区域（5）仅延伸预定距离完成。

9. 发明公开

EP0450389A3 A low-capacitance, high breakdown voltage programmed cell structure for read-only memory circuits 失效
标题翻译：用于只读存储器电路的低电容，高击穿电压编程单元结构
公开(公告)号：EP0450389A3
公开(公告)日：1994-02-23
申请号：EP91104217.4
申请日：1991-03-19
申请人： SGS-THOMSON MICROELECTRONICS S.r.l.
发明人： Ginami, Giancarlo , Laurin, Enrico , Lucherini, Silvia , Vajana, Bruno
IPC分类号： G11C17/12 , H01L27/112
CPC分类号： G11C17/12 , H01L27/112
摘要： A low-capacitance programmed cell structure (1) for read-only memory circuits comprises a field-effect transistor (2) having conventional source (5) and drain (6) regions separated by a channel region (9) overlaid by the gate (11) of the transistor (2). This structure (1) is completed by a so-called channel implant (12) only extending from the source region (5) for a predetermined distance.
摘要翻译：一种用于只读存储器电路的低电容编程单元结构（1）包括场效应晶体管（2），该场效应晶体管具有由沟道区（9）分开的传统源极区（5）和漏极区（6） 11）的晶体管（2）。该结构（1）通过仅从源极区域（5）延伸预定距离的所谓的沟道注入（12）来完成。

10. 发明公开

EP0782196A1 Method of fabricating EEPROM memory devices and EEPROM memory device so formed 失效
标题翻译： HerstellungsverfahrenfürEEPROM-Speicherbauelemente und dadurch hergestellte EEPROM-Speicherbauelemente
公开(公告)号：EP0782196A1
公开(公告)日：1997-07-02
申请号：EP95830544.3
申请日：1995-12-28
申请人： SGS-THOMSON MICROELECTRONICS s.r.l.
发明人： Vajana, Bruno
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： The method includes the steps of growing, astride the surface (15) of a P-type substrate (10), thick field oxide regions (54) delimiting an active area having a width; depositing a thick gate oxide layer (42) on the substrate; forming, over the gate oxide layer, a tunnel mask (59) of photoresist material having a window of a width at least equal to that of the active area; removing the exposed portion of the gate oxide layer; implanting (65) N-type doping species into the substrate through the tunnel mask window to form a continuity region (56); growing a thin tunnel oxide region (55) on the substrate, at the tunnel mask window; depositing a first and second polysilicon layers separated by a dielectric layer; self-align patterning floating gate, control gate and gate oxide regions and one side of the tunnel oxide region; and forming N-type source and drain regions offset laterally in relation to the gate regions; the drain region (13) of the cell overlapping the continuity region (56).
摘要翻译：该方法包括跨越P型衬底（10）的表面（15）的生长步骤，限定具有宽度的有源区域的厚场氧化物区域（54）在衬底上沉积厚栅氧化层（42）; 在所述栅极氧化物层上形成具有至少等于所述有源区的宽度的窗口的光致抗蚀剂材料的隧道掩模（59）; 去除所述栅极氧化物层的暴露部分; 通过隧道掩模窗将（65）N型掺杂物质注入到衬底中以形成连续区域（56）; 在隧道掩模窗上在衬底上生长薄的隧道氧化物区域（55）; 沉积由电介质层分离的第一和第二多晶硅层; 自对准图形浮置栅极，控制栅极和栅极氧化物区域以及隧道氧化物区域的一侧; 以及形成相对于所述栅极区域横向偏移的N型源极和漏极区域; 所述单元的漏极区域（13）与所述连续性区域（56）重叠。

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