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1. 发明授权

EP0893886B1 DEVICE FOR SYNCHRONISING A DIGITAL RECEIVER 失效
标题翻译：用于同步的数字接收机
公开(公告)号：EP0893886B1
公开(公告)日：2005-02-16
申请号：EP96946329.8
申请日：1996-12-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： PARKHOMENKO, Viktor Nikolaevich , RODIONOV, Mikhail Jurievich , LURIE, Mikhail Natanovich
IPC分类号： H03L7/12
CPC分类号： H03L7/10 , H03L7/095 , H03L7/12 , H04L7/033 , Y10S331/02
摘要： The present invention relates to the field of discrete information transmission and more precisely to a device for synchronising a digital receiver. This device reduces the time necessary for the synchronisation and lowers the requirements concerning acceptable errors on frequency and phase shift. The outputs of a digital phase detector (1) are respectively connected to the adding input of an analog adder (2) and to the first information input of a multiplexer (3). The output of the multiplexer is connected to the counting input of the analog adder (2), while the output of said adder (2) is connected through a low-frequency filter to the input of a voltage-controlled generator (5). The output of the generator is connected to the clock input of a decision-making device (6), wherein the information input of said device (6) is connected to the input of the synchronisation device together with the first input of the phase detector (1) and with the first input of a synchronisation state detection unit (7). The second input of the phase detector (1) and the clock input of the decision-making device (6) are connected to the output of the voltage-controlled generator (5). The first output of synchronisation state detection unit (7) is the output indicating the absence of synchronisation and is connected to the control input of the multiplexer (3). The second output of that same unit (7) is the output indicating the synchronisation advance and/or delay and is connected to the second information input of the multiplexer (3).

2. 发明公开

EP0893886A1 DEVICE FOR SYNCHRONISING A DIGITAL RECEIVER 失效
标题翻译： VORRICHTUNG ZUR SYNCHRONIZATION EINES DIGITALENEMPFÄNGERS
公开(公告)号：EP0893886A1
公开(公告)日：1999-01-27
申请号：EP96946329.8
申请日：1996-12-24
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： PARKHOMENKO, Viktor Nikolaevich , RODIONOV, Mikhail Jurievich , LURIE, Mikhail Natanovich
IPC分类号： H03L7/12
CPC分类号： H03L7/10 , H03L7/095 , H03L7/12 , H04L7/033 , Y10S331/02
摘要： The invention relates generally to transmission of digitized information and more specifically to a digital receiver locking device that provides a decreased lock-in time and minimizes requirements to a permissible frequency and phase matching error. Outputs of a digital phase detector 1 are coupled, respectively, to an addition input of an analog adder 2 and a first information input of a multiplexer 3 having an output coupled to a subtraction input of the analog adder 2. An output of the adder 2 is connected via a low-pass filter to an input of a voltage controlled oscillator (VCO) 5 having an output connected to a clock input of a decision unit 6 whose information input is coupled, along with a first input of the phase detector 1 and a first input of a lock state detection circuit 7, to an input of the locking device. A second input of the phase detector 1 and a clock input of the decision unit 6 are coupled to an output of the VCO 5. A first output of the lock state detection circuit 7, which is an unlocked state indication output, is coupled to a control input of the multiplexer 3, and a second output of the circuit 7, which is a lock lead/lag indication output, is coupled to a second information input of the multiplexer 3.
摘要翻译：本发明一般涉及数字化信息的传输，更具体地说涉及一种数字接收机锁定装置，该数字接收机锁定装置提供减少的锁定时间并使对允许的频率和相位匹配误差的要求最小化。数字相位检测器1的输出分别耦合到模拟加法器2的加法输入和耦合到模拟加法器2的减法输入的输出的多路复用器3的第一信息输入。加法器2的输出经由低通滤波器连接到压控振荡器（VCO）5的输入端，该压控振荡器（VCO）5的输出连接到其信息输入耦合的判定单元6的时钟输入以及相位检测器1的第一输入端，以及锁定状态检测电路7的第一输入到锁定装置的输入端。相位检测器1的第二输入端和决定单元6的时钟输入端耦合到VCO5的输出。作为解锁状态指示输出的锁定状态检测电路7的第一输出耦合到多路复用器3的控制输入和作为锁定引导/延迟指示输出的电路7的第二输出耦合到多路复用器3的第二信息输入端。

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