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1. 发明公开

EP2850515A1 FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 有权
标题翻译： FUSION条件写入在指令处理电路和相反条件的处理器系统，方法和计算机可读媒体指令
公开(公告)号：EP2850515A1
公开(公告)日：2015-03-25
申请号：EP13724143.6
申请日：2013-05-16
申请人： Qualcomm Incorporated
发明人： BROWN, Melinda J. , DIEFFENDERFER, James Norris , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , IRWIN, Andrew S. , MORROW, Michael William
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/30072 , G06F9/3017
摘要： Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.
摘要翻译：熔合具有指令处理电路和相关的处理器的系统，方法，和计算机可读介质相反条件的有条件写入指令是游离缺失盘。在一个实施方式中，写入基于评估第一条件的第一值到目标寄存器的第一有条件写入指令是通过在指令处理电路检测到。因此，该电路检测第二有条件写入指令写入基于评估第二条件做了第二值到目标寄存器在第一条件的逻辑相反。所述第一条件或第二条件被选择为稠合的指令条件，和相应的值被选择为，如果为真，并且如果假值。为如果真值选择性地写入到目标寄存器，如果融合指令条件评估为真，并且选择性地将如果假值写入到目标寄存器，如果融合指令条件评估为假时产生的融合指令。

2. 发明公开

EP2137611A1 SYSTEM, METHOD AND SOFTWARE TO PRELOAD INSTRUCTIONS FROM AN INSTRUCTION SET OTHER THAN ONE CURRENTLY EXECUTING 有权
标题翻译：系统，方法和软件指令从预充电从刚刚执行各种指令集
公开(公告)号：EP2137611A1
公开(公告)日：2009-12-30
申请号：EP08732245.9
申请日：2008-03-14
申请人： Qualcomm Incorporated
发明人： SARTORIUS, Thomas Andrew , STEMPEL, Brian Michael , SMITH, Rodney Wayne
IPC分类号： G06F9/318 , G06F9/38 , G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.

3. 发明公开

EP1904922A2 POWER SAVING METHODS AND APPARATUS FOR VARIABLE LENGTH INSTRUCTIONS 失效
标题翻译：节能方法和设备指令的变量长度
公开(公告)号：EP1904922A2
公开(公告)日：2008-04-02
申请号：EP06736989.2
申请日：2006-03-03
申请人： QUALCOMM INCORPORATED
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SMITH, Rodney Wayne , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/30
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.

4. 发明授权

EP2972789B8 METHOD TO IMPROVE SPEED OF EXECUTING RETURN BRANCH INSTRUCTIONS IN A PROCESSOR 有权
公开(公告)号：EP2972789B8
公开(公告)日：2020-03-04
申请号：EP14720842.5
申请日：2014-03-14
申请人： QUALCOMM Incorporated
发明人： SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , BROWN, Melinda J. , STREETT, Daren Eugene
IPC分类号： G06F9/30 , G06F9/38

5. 发明公开

EP2972791A1 METHOD AND APPARATUS FOR FORWARDING LITERAL GENERATED DATA TO DEPENDENT INSTRUCTIONS MORE EFFICIENTLY USING A CONSTANT CACHE 审中-公开
标题翻译：正向以书面形式方法和装置生成指令方面的数据提高了工作效率采用恒定高速缓存存储器
公开(公告)号：EP2972791A1
公开(公告)日：2016-01-20
申请号：EP14724200.2
申请日：2014-03-14
申请人： Qualcomm Incorporated
发明人： DIEFFENDERFER, James Norris , MORROW, Michael William , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , HIGDON, Daniel S. , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , KOTHARI, Kulin Narendra
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3832 , G06F9/30032 , G06F9/3828
摘要： A processor to a store constant value (immediate or literal) in a cache upon decoding a move immediate instruction in which the immediate is to be moved (copied or written) to an architected register. The constant value is stored in an entry in the cache. Each entry in the cache includes a field to indicate whether its stored constant value is valid, and a field to associate the entry with an architected register. Once a constant value is stored in the cache, it is immediately available for forwarding to a processor pipeline where a decoded instruction may need the constant value as an operand.
摘要翻译：处理器，用于根据解码的移动立即指令，其中所述即时是在结构寄存器被移动（拷贝或写）存储在高速缓存中的恒定值（立即或文字）。恒定值存储在缓存中的项目。高速缓存中的每个条目都包含一个字段，表示无论其储存的恒定值是有效的，并且场与架构寄存器中的条目相关联。一旦一个恒定值被存储在缓存中，它可立即转发到处理器管线，其中经解码的指令可能需要恒定值作为操作数。

6. 发明授权

EP2018609B1 PRE-DECODING VARIABLE LENGTH INSTRUCTIONS 有权
标题翻译：预译码不同长度COMMANDS
公开(公告)号：EP2018609B1
公开(公告)日：2010-12-29
申请号：EP07760992.3
申请日：2007-04-20
申请人： QUALCOMM Incorporated
发明人： SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： G06F9/30 , G06F9/318
CPC分类号： G06F9/30149 , G06F9/30152 , G06F9/30185 , G06F9/30192 , G06F9/3802 , G06F9/382
摘要： A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.

7. 发明公开

EP1999576A1 METHOD AND APPARATUS FOR REPAIRING A LINK STACK 审中-公开
标题翻译：方法和设备修复用复合桩
公开(公告)号：EP1999576A1
公开(公告)日：2008-12-10
申请号：EP07757575.1
申请日：2007-02-27
申请人： QUALCOMM Incorporated
发明人： DIEFFENDERFER, James Norris , MANDZAK, David John , SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30054 , G06F9/3806 , G06F9/3842 , G06F9/3861
摘要： A link stack in a processor is repaired in response to a procedure return address misprediction error. In one example, a link stack for use in a processor is repaired by detecting an error in a procedure return address value retrieved from the link stack and skipping a procedure return address value currently queued for retrieval from the link stack responsive to detecting the error. In one or more embodiments, a link stack circuit comprises a link stack and a link stack pointer. The link stack is configured to store a plurality of procedure return address values. The link stack pointer is configured to skip a procedure return address value currently queued for retrieval from the link stack responsive to an error detected in a procedure return address value previously retrieved from the link stack.

8. 发明公开

EP1886217A2 CACHING INSTRUCTIONS FOR A MULTIPLE-STATE PROCESSOR 审中-公开
标题翻译： LATCH命令来与几个国家的处理器
公开(公告)号：EP1886217A2
公开(公告)日：2008-02-13
申请号：EP06770878.4
申请日：2006-05-18
申请人： Qualcomm Incorporated
发明人： SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： G06F9/38 , G06F9/318
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A block of instructions may be retrieved from memory while the processor is operating in one of the states. The instructions may be pre-decoded in accordance with said one of the states and loaded into cache. The processor, or another entity, may be used to determine whether the current state of the processor is the same as said one of the states used to pre-decode the instructions when one of the pre-decoded instructions in the cache is needed by the processor.

9. 发明授权

EP1886217B1 CACHING INSTRUCTIONS FOR A MULTIPLE-STATE PROCESSOR 有权
公开(公告)号：EP1886217B1
公开(公告)日：2018-08-01
申请号：EP06770878.4
申请日：2006-05-18
申请人： Qualcomm Incorporated
发明人： SMITH, Rodney Wayne , STEMPEL, Brian Michael
IPC分类号： G06F9/38 , G06F9/318
CPC分类号： G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： A method and apparatus for caching instructions for a processor having multiple operating states. At least two of the operating states of the processor supporting different instruction sets. A block of instructions may be retrieved from memory while the processor is operating in one of the states. The instructions may be pre-decoded in accordance with said one of the states and loaded into cache. The processor, or another entity, may be used to determine whether the current state of the processor is the same as said one of the states used to pre-decode the instructions when one of the pre-decoded instructions in the cache is needed by the processor.

10. 发明公开

EP3198400A1 DEPENDENCY-PREDICTION OF INSTRUCTIONS 有权
标题翻译：依从性 - 预测的指示
公开(公告)号：EP3198400A1
公开(公告)日：2017-08-02
申请号：EP15771804.0
申请日：2015-09-08
申请人： Qualcomm Incorporated
发明人： STEMPEL, Brian Michael , DIEFFENDERFER, James Norris , MCILVAINE, Michael Scott , BROWN, Melinda
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30072 , G06F9/30149 , G06F9/38 , G06F9/3836 , G06F9/3842 , G06F9/3885
摘要： Systems and methods for dependency-prediction include executing instructions in an instruction pipeline of a processor and detecting a conditionality-imposing control instruction, such as an If-Then (IT) instruction, which imposes dependent behavior on a conditionality block size of one or more dependent instructions. Prior to executing a first instruction, a dependency-prediction is made to determine if the first instruction is a dependent instruction of the conditionality-imposing control instruction, based on the conditionality block size and one or more parameters of the instruction pipeline. The first instruction is executed based on the dependency-prediction. When the first instruction is dependency-mispredicted, an associated dependency-misprediction penalty is mitigated. If the first instruction is a branch instruction, the mitigation involves training a branch prediction tracking mechanism to correctly dependency-predict future occurrences of the first instruction.
摘要翻译：用于依赖性预测的系统和方法包括在处理器的指令流水线中执行指令并检测强制性条件性控制指令，诸如If-Then（IT）指令，其将一个或多个条件性块的大小依赖指令。在执行第一指令之前，基于条件性块大小和指令流水线的一个或多个参数进行依赖性预测，以确定第一指令是否是条件性施加控制指令的依赖性指令。第一条指令是基于依赖关系预测执行的。当第一条指令是依赖性错误预测时，相关的依赖性错误预测惩罚将得到缓解。如果第一指令是分支指令，则缓解涉及训练分支预测追踪机制以正确地依从性预测第一指令的未来出现。

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