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1. 发明公开

EP4292040A1 METHODS AND APPARATUS FOR TENSOR OBJECT SUPPORT IN MACHINE LEARNING WORKLOADS 审中-实审
公开(公告)号：EP4292040A1
公开(公告)日：2023-12-20
申请号：EP22704032.6
申请日：2022-01-12
申请人： QUALCOMM INCORPORATED
发明人： KAMENETSKAYA, Elina , LI, Liang , GRUBER, Andrew Evan , LEGER, Jeffrey , CALIDAS, Balaji , ZHANG, Ruihao
IPC分类号： G06T1/60 , G06T1/20 , G06N3/02 , G06N20/00

2. 发明公开

EP4242972A3 METHODS AND APPARATUS FOR EDGE COMPRESSION ANTI-ALIASING 审中-实审
公开(公告)号：EP4242972A3
公开(公告)日：2023-11-22
申请号：EP23179211.0
申请日：2021-02-09
申请人： Qualcomm Incorporated
发明人： GRUBER, Andrew Evan , GUMMIDIPUDI, Krishnaiah , AKKARAJU, Pavan Kumar , BHIRAVABHATLA, Kalyan Kumar , SINGH, Ankit Kumar , RAJ, Sharad
IPC分类号： G06T15/50 , G06T15/00
摘要： The present disclosure relates to methods and apparatus for graphics processing. The present disclosure can calculate a center-edge distance of a first pixel, the center-edge distance of the first pixel equal to a distance from a first pixel center to one or more edges of a first primitive. Additionally, the present disclosure can store the center-edge distance of the first pixel when the first primitive is visible in a scene. The present disclosure can also determine an amount of overlap between the first pixel and the first primitive. Further, the present disclosure can blend a color of the first pixel with a color of a second pixel based on at least one of the center-edge distance of the first pixel or the amount of overlap between the first pixel and the first primitive.

3. 发明公开

EP4248411A1 METHODS AND APPARATUS FOR SELECTION OF RENDERING MODES 审中-实审
公开(公告)号：EP4248411A1
公开(公告)日：2023-09-27
申请号：EP20961874.3
申请日：2020-11-18
申请人： QUALCOMM INCORPORATED
发明人： ALLA, Srihari Babu , NAGENDRA KUMAR, Jonnala Gadda , SEETHARAMAIAH, Avinash , GRUBER, Andrew Evan , FRISINGER, Thomas Edwin , HAMMERSTONE, Richard H. , DU, Bo , XU, Yongjun
IPC分类号： G06T15/04 , G06T15/06 , G06T11/40

4. 发明公开

EP4238050A1 FAST INCREMENTAL SHARED CONSTANTS 审中-实审
公开(公告)号：EP4238050A1
公开(公告)日：2023-09-06
申请号：EP21806436.8
申请日：2021-09-28
申请人： QUALCOMM INCORPORATED
发明人： FRISINGER, Thomas Edwin , HAMMERSTONE, Richard , GRUBER, Andrew Evan , ZHONG, Gang , DU, Yun , NAGENDRA KUMAR, Jonnala Gadda
IPC分类号： G06T1/20

5. 发明授权

EP3183646B1 SKIPPING OF DATA STORAGE 有权
公开(公告)号：EP3183646B1
公开(公告)日：2018-07-25
申请号：EP15751211.2
申请日：2015-08-04
申请人： Qualcomm Incorporated
发明人： DU, Yun , CHEN, Lin , GRUBER, Andrew Evan , ZHANG, Chihong , YU, Chun
IPC分类号： G06F9/38
CPC分类号： G06F9/30098 , G06F8/441 , G06F9/30145 , G06F9/30181 , G06F9/3828 , G06F9/3859 , G06T1/20 , G06T2200/28
摘要： Techniques are described in which an indication is included to indicate a last use of an intermediate value generated as part of determining a final value is not be stored in a general purpose register (GPR). A processing unit avoids storing the intermediate value in the GPR based on the indication because the intermediate value is no longer needed for determining the final value.

6. 发明授权

EP3044754B1 FAULT-TOLERANT PREEMPTION MECHANISM AT ARBITRARY CONTROL POINTS FOR GRAPHICS PROCESSING 有权
标题翻译：图形处理任意控制点的容错预取机制
公开(公告)号：EP3044754B1
公开(公告)日：2018-01-17
申请号：EP14777214.9
申请日：2014-09-05
申请人： Qualcomm Incorporated
发明人： FRASCATI, Christopher Paul , BALCI, Murat , SEETHARAMAIAH, Avinash , GRUBER, Andrew Evan , BOURD, Alexei Vladimirovich
IPC分类号： G06T1/20 , G06T1/60 , G06F9/48
CPC分类号： G09G5/399 , G06F9/46 , G06F9/4843 , G06F2209/483 , G06F2209/509 , G06T1/20 , G06T1/60
摘要： This disclosure presents techniques and structures for preemption at arbitrary control points in graphics processing. A method of graphics processing may comprise executing commands in a command buffer, the commands operating on data in a read-modify-write memory resource, double buffering the data in the read-modify-write memory resource, such that a first buffer stores original data of the read-modify-write memory resource and a second buffer stores any modified data produced by executing the commands in the command buffer, receiving a request to preempt execution of the commands in the command buffer before completing all commands in the command buffer, and restarting execution of the commands at the start of the command buffer using the original data in the first buffer.

7. 发明公开

EP3183645A1 EMULATION OF FUSED MULTIPLY-ADD OPERATIONS 审中-公开
标题翻译：融合多项式加法运算的仿真
公开(公告)号：EP3183645A1
公开(公告)日：2017-06-28
申请号：EP15748386.8
申请日：2015-07-27
申请人： Qualcomm Incorporated
发明人： ARGADE, Pramod Vasant , GRUBER, Andrew Evan , HO, Chiente , HALL, Stewart Griffin , CHEN, Lin
IPC分类号： G06F7/483 , G06F7/544
CPC分类号： G06F7/5443 , G06F5/01 , G06F7/483 , G06F7/57
摘要： At least one processor may emulate a fused multiply-add operation for a first operand, a second operand, and a third operand. The at least one processor may determine an intermediate value based at least in part on multiplying the first operand with the second operand, determine at least one of an upper intermediate value or a lower intermediate value, wherein determining the upper intermediate value comprises rounding, towards zero, the intermediate value by a specified number of bits, and wherein determining the lower intermediate value comprises subtracting the intermediate value by the upper intermediate value, determine an upper value and a lower value based at least in part on adding or subtracting the third operand to one of the upper intermediate value or the lower intermediate value, and determine an emulated fused multiply-add result by adding the upper value and the lower value.
摘要翻译：至少一个处理器可以模拟第一操作数，第二操作数和第三操作数的融合乘加操作。至少一个处理器可以至少部分地基于将第一操作数与第二操作数相乘来确定中间值，确定上中间值或下中间值中的至少一个，其中确定上中间值包括舍入所述中间值乘以指定的位数，并且其中确定所述较低中间值包括通过所述较高中间值减去所述中间值，至少部分地基于增加或减去所述第三操作数来确定较高值和较低值到较高中间值或较低中间值中的一个，并且通过将较高值和较低值相加来确定模拟融合乘加结果。

8. 发明公开

EP3170069A1 VECTOR SCALING INSTRUCTIONS FOR USE IN AN ARITHMETIC LOGIC UNIT 有权
标题翻译：用于算术逻辑单元的矢量缩放指令
公开(公告)号：EP3170069A1
公开(公告)日：2017-05-24
申请号：EP15736718.6
申请日：2015-06-22
申请人： Qualcomm Incorporated
发明人： CHEN, Lin , GRUBER, Andrew Evan , JIAO, Guofang , HO, Chiente , ARGADE, Pramod Vasant
IPC分类号： G06F7/552 , G09C1/00
CPC分类号： G06F7/49936 , G06F7/552 , G06F2207/5525 , G09C1/00 , H04L2209/12
摘要： At least one processor may receive components of a vector, wherein each of the components of the vector comprises at least an exponent. The at least one processor may further determine a maximum exponent out of respective exponents of the components of the vector, and may determine a scaling value based at least in part on the maximum exponent. An arithmetic logic unit of the at least one processor may scale the vector, by subtracting the scaling value from each of the respective exponents of the components of the vector.
摘要翻译：至少一个处理器可以接收向量的分量，其中向量的每个分量包括至少一个指数。所述至少一个处理器可以进一步确定矢量的各个分量的指数中的最大指数，并且可以至少部分地基于最大指数来确定缩放值。至少一个处理器的算术逻辑单元可以通过从矢量的各个分量的各个指数中减去缩放值来缩放矢量。

9. 发明公开

EP3061070A2 SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING 有权
标题翻译：于执行分级结构Z剔除部分覆盖瓦片选择性归并
公开(公告)号：EP3061070A2
公开(公告)日：2016-08-31
申请号：EP14789461.2
申请日：2014-10-08
申请人： Qualcomm Incorporated
发明人： WANG, Tao , GRUBER, Andrew Evan , KHANDELWAL, Shambhoo
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/405 , G06T1/60 , G06T15/005
摘要： This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.
摘要翻译：本发明描述用于执行分级结构Z剔除在图形处理系统。在一些实例中，所述技术用于执行分级结构Z剔除可以涉及选择性地合并部分覆盖源瓦片用于图块位置为基于一个完全覆盖的合并源瓦是否对所述部分覆盖的源瓦片保守最远z值比用于图块位置的剔除z值越接近，并且使用与所述完全覆盖的合并源块相关联的一个保守的最远z值来更新剔除ž 对于瓷砖的位置值。在另外的实例中，用于执行分级结构Z剔除可使用高速缓存单元的技术并没有与在底层存储器相关联来存储保守最远z值和覆盖遮罩用于合并源瓷砖。所述高速缓存单元的容量可以比为所有瓦片位置存储在一个渲染目标合并源瓦片数据所需高速缓存的大小要小。

10. 发明公开

EP4371074A1 OPTIMIZATION OF DEPTH AND SHADOW PASS RENDERING IN TILE BASED ARCHITECTURES 审中-实审
公开(公告)号：EP4371074A1
公开(公告)日：2024-05-22
申请号：EP22744346.2
申请日：2022-06-15
申请人： QUALCOMM INCORPORATED
发明人： KURUMANGHAT, Sreyas , BHIRAVABHATLA, Kalyan Kumar , GRUBER, Andrew Evan , WANG, Tao , YANG, Baoguang , AKKARAJU, Pavan Kumar
IPC分类号： G06T15/00 , G06T15/40
CPC分类号： G06T15/005 , G06T15/405

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