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1. 发明公开

EP4238220A1 MISMATCH AND TIMING CORRECTION TECHNIQUE FOR MIXING-MODE DIGITAL-TO-ANALOG CONVERTER (DAC) 审中-实审
公开(公告)号：EP4238220A1
公开(公告)日：2023-09-06
申请号：EP21805816.2
申请日：2021-10-13
申请人： QUALCOMM INCORPORATED
发明人： LIU, Xilin , MAHMOUDIDARYAN, Parisa , MEHDIZAD TALEIE, Shahin , RASHIDI, Negar , SEO, Dongwon
IPC分类号： H03M1/10 , H03K5/05 , H03K5/156 , H03M1/66 , H03K5/00

2. 发明授权

EP3146628B1 DIFFERENTIAL MODE BANDWIDTH EXTENSION TECHNIQUE WITH COMMON MODE COMPENSATION 有权
公开(公告)号：EP3146628B1
公开(公告)日：2020-01-01
申请号：EP15727107.3
申请日：2015-05-07
申请人： Qualcomm Incorporated
发明人： KONG, Derui , LEE, Sang Min , MCGOWAN, Michael Joseph , SEO, Dongwon
IPC分类号： H03F1/14 , H03F3/45

3. 发明授权

EP2759107B1 LOAD DETECTING IMPEDANCE MATCHING BUFFER 有权
标题翻译：负载检测阻抗匹配缓冲器
公开(公告)号：EP2759107B1
公开(公告)日：2018-03-14
申请号：EP12780935.8
申请日：2012-09-24
申请人： Qualcomm Incorporated
发明人： CHIABURU, Liviu , TALEIE, Shahin Medhizah , SEO, Dongwon , SILVERSTEIN, Roy B.
IPC分类号： H04L25/02
CPC分类号： H04L25/0278
摘要： A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.

4. 发明公开

EP2965431A1 LOW GLITCH-NOISE DAC 有权
标题翻译： DAC MIT NIEDRIGEMSTÖRUNGSRAUSCHEN
公开(公告)号：EP2965431A1
公开(公告)日：2016-01-13
申请号：EP14713304.5
申请日：2014-03-04
申请人： Qualcomm Incorporated
发明人： SEO, Dongwon , LEE, Sang Min
IPC分类号： H03M1/08 , H03M1/68 , H03M1/74 , H03M1/78
CPC分类号： H03M1/785 , H03M1/0863 , H03M1/687 , H03M1/747
摘要： An N-bit digital-to-analog converter (DAC) includes N input stages each of which generates the same amount of current and includes a pair of similarly sized transistor switches responsive to differential bits. The 2M−1 input stages associated with the M most significant bits of the DAC are connected in parallel and deliver their currents differentially to the DAC's current summing nodes. Each of the remaining (N−M) stages includes a resistive network that supplies a current defined by a binary weight of the stage's bit position within the DAC. The (N−M) stages deliver their currents to the current summing nodes differentially. The DAC further includes an impedance attenuator adapted to maintain the impedance of the current summing nodes and the voltage difference between the current summing nodes within a range defined by a gain of a differential amplifier disposed in the impedance attenuator.
摘要翻译： N位数模转换器（DAC）包括N个输入级，每个输入级产生相同的电流量，并且包括响应于差分位的一对类似尺寸的晶体管开关。与DAC的M个最高有效位相关联的2M-1个输入级并联连接，并将其电流差分地传递给DAC的当前求和节点。剩余的（N-M）级中的每一个包括电阻网络，其提供由DAC内的级的位位置的二进制权重定义的电流。（N-M）级将电流差分地传递给当前求和节点。 DAC进一步包括阻抗衰减器，其适于在由设置在阻抗衰减器中的差分放大器的增益限定的范围内保持电流求和节点的阻抗和电流求和节点之间的电压差。

5. 发明授权

EP2269311B1 APPARATUS AND METHOD FOR DYNAMIC CIRCUIT ELEMENT SELECTION IN A DIGITAL-TO-ANALOG CONVERTER 有权
标题翻译：装置和方法的动态电路元件选择用在数字模拟转换器
公开(公告)号：EP2269311B1
公开(公告)日：2012-06-20
申请号：EP09762966.1
申请日：2009-03-08
申请人： QUALCOMM Incorporated
发明人： SEO, Dongwon , McALLISTER, Gene H. , DABAG, Hayg-Taniel
IPC分类号： H03M1/06 , H03M1/00
CPC分类号： H03M1/004 , H03M1/066 , H03M1/0665 , H03M1/0673 , H03M1/74 , H03M3/502
摘要： According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

6. 发明公开

EP2193603A1 HIGH-SWING OPERATIONAL AMPLIFIER OUTPUT STAGE USING ADAPTIVE BIASING 审中-公开
标题翻译：大信号摆幅运算放大器输出级使用自适应偏置
公开(公告)号：EP2193603A1
公开(公告)日：2010-06-09
申请号：EP08828033.4
申请日：2008-08-21
申请人： QUALCOMM Incorporated
发明人： DABAG, Hayg , SEO, Dongwon , MISHRA, Manu
IPC分类号： H03F3/30 , H03F3/45 , H03F1/52
CPC分类号： H03F3/45192 , H03F1/52 , H03F1/523 , H03F3/303 , H03F2203/30015 , H03F2203/30084 , H03F2203/30117 , H03F2203/45244 , H03F2203/45626 , H03F2203/45732
摘要： An output stage (123) includes two transistors (T3, T4) (switching transistor, and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, (120) and also includes two transistors (Tl, T2) (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node (121) and a ground node. Providing the biasing transistors (T2,T4) reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit (26) adjusts the gate voltage on a biasing transistor (T2,T4) based on the output node (121) voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

7. 发明公开

EP4409747A1 DIGITAL-TO-ANALOG CONVERTER CALIBRATION USING ERROR DACS 审中-公开
公开(公告)号：EP4409747A1
公开(公告)日：2024-08-07
申请号：EP22783251.6
申请日：2022-09-09
申请人： QUALCOMM INCORPORATED
发明人： TANG, Zhilong , SEO, Dongwon
IPC分类号： H03M1/10 , H03M1/74
CPC分类号： H03M1/742 , H03M1/1061

8. 发明公开

EP4364298A1 DIGITAL AMPLITUDE TRACKING CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER 审中-实审
公开(公告)号：EP4364298A1
公开(公告)日：2024-05-08
申请号：EP22733847.2
申请日：2022-06-01
申请人： QUALCOMM INCORPORATED
发明人： MEHDIZAD TALEIE, Shahin , SEO, Dongwon , SWAMINATHAN, Ashok , SAHOTA, Gurkanwal Singh , WEIL, Andrew , FEI, Haibo
IPC分类号： H03M1/74 , H03M1/12 , H03M1/78
CPC分类号： H03M1/742 , H03M1/785 , H03M1/002 , H03M1/1295

9. 发明公开

EP3198355A1 VOLTAGE-TO-CURRENT CONVERTER 审中-公开
标题翻译：电压至电流转换器
公开(公告)号：EP3198355A1
公开(公告)日：2017-08-02
申请号：EP15775893.9
申请日：2015-09-24
申请人： Qualcomm Incorporated
发明人： DU, Li , LEE, Sang Min , SEO, Dongwon
IPC分类号： G05F1/56
CPC分类号： H03G3/3042 , G05F1/561 , H03F1/0233 , H03F3/193 , H03F3/21 , H03F2200/21 , H03F2200/252 , H03F2200/451 , H03K5/24
摘要： A converter including: an amplifier having first and second input terminals and an output terminal, the first input terminal configured to receive a reference voltage; an array of resistors configured to generate a tuning voltage; and a first plurality of switches coupled to the second input terminal of the amplifier and the array of resistors, the first plurality of switches configured to adjust a gain of the amplifier by selecting at least one resistor in the array of resistors to connect to the second input terminal of the amplifier.
摘要翻译： A转换器，包括：具有第一和第二输入端子和输出端子的放大器，所述第一输入端子被配置为接收参考电压; 被配置为产生调谐电压的电阻器阵列; 以及耦合到所述放大器的所述第二输入端子和所述电阻器阵列的第一多个开关，所述第一多个开关经配置以通过选择所述电阻器阵列中的至少一个电阻器来调整所述放大器的增益以连接到所述第二放大器的输入端子。

10. 发明授权

EP2151057B1 CIRCUIT AND METHOD FOR DYNAMICALLY SELECTING CIRCUIT ELEMENTS 有权
标题翻译：电路及方法的电路元件的动态选择
公开(公告)号：EP2151057B1
公开(公告)日：2012-02-15
申请号：EP08769279.4
申请日：2008-05-02
申请人： QUALCOMM Incorporated
发明人： DABAG, Hayg-Taniel , MCALLISTER, Gene, H. , SEO, Dongwon
IPC分类号： H03M1/06 , H03M1/74
CPC分类号： H03M1/0665 , H03M1/0673 , H03M1/74 , H03M3/502
摘要： Techniques for dynamically selecting circuit elements to combat mismatches are described. In one design, an apparatus includes first, second, and third circuits. The first circuit receives input data and provides first signals that are asserted based on the input data, e.g., with thermometer decoding. The second circuit receives the first signals and provides second signals used to select circuit elements, e.g., current sources, capacitors, resistors, etc. The third circuit generates a control for the second circuit, and the second circuit maps the first signals to the second signals based on this control. In one design, the second circuit includes a set of multiplexers and a control circuit. The multiplexers provides the first signals, circularly rotated by an amount determined by the control, as the second signals. The control circuit accumulates control data (e.g., the input data, pseudo-random data, or a fixed value) with the current control value to obtain new control value.

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