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1. 发明授权

EP3218868B1 DYNAMIC PIPELINE FOR GRAPHICS PROCESSING 有权
公开(公告)号：EP3218868B1
公开(公告)日：2019-11-20
申请号：EP15788512.0
申请日：2015-10-15
申请人： Qualcomm Incorporated
发明人： LI, Liang , GRUBER, Andrew Evan , JIAO, Guofang , QI, Zhenyu , PITARYS, Gregory Steve , NOLAN, Scott William
IPC分类号： G06T1/20

2. 发明公开

EP3465606A1 PER-SHADER PREAMBLE FOR GRAPHICS PROCESSING 审中-公开
公开(公告)号：EP3465606A1
公开(公告)日：2019-04-10
申请号：EP17720913.7
申请日：2017-04-10
申请人： QUALCOMM Incorporated
发明人： CHEN, Lin , DU, Yun , GRUBER, Andrew Evan , JIAO, Guofang , YU, Chun , GARCIA GARCIA, David Rigel
IPC分类号： G06T1/20

3. 发明公开

EP3161817A1 LOAD SCHEME FOR SHARED REGISTER IN GPU 有权
标题翻译： GPU中共享寄存器的加载方案
公开(公告)号：EP3161817A1
公开(公告)日：2017-05-03
申请号：EP15739043.6
申请日：2015-06-11
申请人： Qualcomm Incorporated
发明人： DU, Yun , GRUBER, Andrew Evan , CHEN, Lin , JIAO, Guofang , YU, Chun
IPC分类号： G09G5/36 , G06T1/60
CPC分类号： G06T1/60 , G06T15/80 , G09G5/363 , G09G2352/00 , G09G2360/06
摘要： Techniques are described for determining whether data of a variable for each of a plurality of graphics items is same. If determined that the data is the same, the techniques store the data in a storage location of a specialized shared general purpose register that is associated with the variable.
摘要翻译：描述了用于确定多个图形项目中的每一个的变量的数据是否相同的技术。如果确定数据是相同的，则这些技术将数据存储在与变量相关联的专用共享通用寄存器的存储位置中。

4. 发明公开

EP2593862A1 OUT-OF-ORDER COMMAND EXECUTION IN A MULTIMEDIA PROCESSOR 有权
标题翻译： OUT-OF-ORDER命令的多媒体处理器EXECUTION
公开(公告)号：EP2593862A1
公开(公告)日：2013-05-22
申请号：EP11735958.8
申请日：2011-07-15
申请人： Qualcomm Incorporated , Jiao, Guofang
发明人： JIAO, Guofang , BOURD, Alexei, V.
IPC分类号： G06F9/38 , G06T1/20
CPC分类号： G06F9/3885 , G06F9/3838 , G06T1/20
摘要： Techniques are described for reordering commands to improve the speed at which at least one command stream may execute. Prior to distributing commands in the at least one command stream to multiple pipelines, a multimedia processor analyzes any inter-pipeline dependencies and determines the current execution state of the pipelines. The processor may, based on this information, reorder the at least one command stream by prioritizing commands that lack any current dependencies and therefore may be executed immediately by the appropriate pipeline. Such out of order execution of commands in the at least one command stream may increase the throughput of the multimedia processor by increasing the rate at which the command stream is executed.

5. 发明公开

EP2366173A2 DISCARDING OF VERTEX POINTS DURING TWO-DIMENSIONAL GRAPHICS RENDERING USING THREE-DIMENSIONAL GRAPHICS HARDWARE 审中-公开
标题翻译：顶点期间三维图形播放DISCARD利用三维图形硬件
公开(公告)号：EP2366173A2
公开(公告)日：2011-09-21
申请号：EP09799787.8
申请日：2009-12-07
申请人： QUALCOMM Incorporated
发明人： BOURD, Alexei, V. , JIAO, Guofang , YUN, Jay, Chunsup
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： This disclosure describes techniques for removing vertex points during two dimensional (2D) graphics rendering using three-dimensional (3D) graphics hardware. In accordance with the described techniques one or more vertex points may be removed during 2D graphics rendering using 3D graphics hardware. For example, the techniques may remove redundant vertex points in the display coordinate space by discarding vertex points that have the substantially same positional coordinates in the display coordinate space as a previous vertex point. Alternatively or additionally, the techniques may remove excess vertex points that lie in a straight line. Removing the redundant vertex points or vertex points that lie in a straight line allow for more efficient utilization of the hardware resources of the GPU and increase the speed at which the GPU renders the image for display.

6. 发明公开

EP2269172A1 MULTI-STAGE TESSELLATION FOR GRAPHICS RENDERING 审中-公开
标题翻译：用于图形渲染的多级折叠
公开(公告)号：EP2269172A1
公开(公告)日：2011-01-05
申请号：EP09723358.9
申请日：2009-03-19
申请人： QUALCOMM Incorporated
发明人： WEI, Jian , JIAO, Guofang , BI, Ning , WU, Chehui
IPC分类号： G06T11/20
CPC分类号： G06T11/203
摘要： This disclosure describes a multi-stage tessellation technique for tessellating a curve during graphics rendering. In particular, a first tessellation stage tessellates the curve into a first set of line segments that each represents a portion of the curve. A second tessellation stage further tessellates the portion of the curve represented by each of the line segments of the first set into additional line segments that more finely represent the shape of the curve. In this manner, each portion of the curve that was represented by only one line segment after the first tessellation stage is represented by more than one line segment after the second tessellation stage. In some instances, more than two tessellation stages may be performed to tessellate the curve.
摘要翻译：本公开描述了用于在图形呈现期间细分曲线的多阶段细分技术。特别地，第一曲面细分阶段将曲线镶嵌成第一组线段，其分别代表曲线的一部分。第二曲面细分阶段进一步将由第一组的每个线段表示的曲线部分细分为更精细地表示曲线形状的附加线段。以这种方式，在第一曲面细分阶段之后仅由一个线段表示的曲线的每个部分在第二曲面细分阶段之后由多于一个线段表示。在一些情况下，可以执行多于两个镶嵌阶段以镶嵌曲线。

7. 发明公开

EP2084670A2 GRAPHICS PROCESSING UNIT WITH SHARED ARITHMETIC LOGIC UNIT 审中-公开
标题翻译：图形处理单元的单元共享算术逻辑
公开(公告)号：EP2084670A2
公开(公告)日：2009-08-05
申请号：EP07854073.9
申请日：2007-10-15
申请人： QUALCOMM Incorporated
发明人： JIAO, Guofang , RUTTENBERG, Brian , YU, Chun , DU, Yun
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： This disclosure describes a graphics processing unit (GPU) pipeline that uses one or more shared arithmetic logic units (ALUs). In order to facilitate such sharing of ALUs, the stages of the disclosed GPU pipeline may be rearranged relative to conventional GPU pipelines. In addition, by rearranging the stages of the GPU pipeline, efficiencies may be achieved in the image processing. Unlike conventional GPU pipelines, for example, an attribute gradient setup stage can be located much later in the pipeline, and the attribute interpolator stage may immediately follow the attribute gradient setup stage. This allows sharing of an ALU by the attribute gradient setup and attribute interpolator stages. Several other techniques and features for the GPU pipeline are also described, which may improve performance and possibly achieve additional processing efficiencies.

8. 发明公开

EP2024819A2 GRAPHICS PROCESSOR WITH ARITHMETIC AND ELEMENTARY FUNCTION UNITS 有权转让
标题翻译：算术和基本功能单元图形处理器
公开(公告)号：EP2024819A2
公开(公告)日：2009-02-18
申请号：EP07797797.3
申请日：2007-05-25
申请人： Qualcomm Incorporated
发明人： BOURD, Alexei, V. , DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F9/38 , G06T1/20
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.

9. 发明公开

EP3218868A1 DYNAMIC PIPELINE FOR GRAPHICS PROCESSING 有权
标题翻译：用于图形处理的动态管道
公开(公告)号：EP3218868A1
公开(公告)日：2017-09-20
申请号：EP15788512.0
申请日：2015-10-15
申请人： Qualcomm Incorporated
发明人： LI, Liang , GRUBER, Andrew Evan , JIAO, Guofang , QI, Zhenyu , PITARYS, Gregory Steve , NOLAN, Scott William
IPC分类号： G06T1/20
摘要： This disclosure describes an apparatus configured to process graphics data. The apparatus may include a fixed hardware pipeline configured to execute one or more functions on a current set of graphics data. The fixed hardware pipeline may include a plurality of stages including a bypassable portion of the plurality of stages. The apparatus may further include a shortcut circuit configured to route the current set of graphics data around the bypassable portion of the plurality of stages, and a controller positioned before the bypassable portion of the plurality of stages, the controller configured to selectively route the current set of graphics data to one of the shortcut circuit or the bypassable portion of the plurality of stages.
摘要翻译：本公开描述了被配置为处理图形数据的装置。该装置可以包括被配置为对当前图形数据集执行一个或多个功能的固定硬件流水线。固定硬件流水线可以包括多个级，所述多个级包括多个级中的可旁路部分。该设备可以进一步包括被配置为在多个级的可绕过部分周围路由当前图形数据集的快捷方式电路以及位于多个级的可绕过部分之前的控制器，控制器被配置为选择性地路由电流集将图形数据提供给多个级的快捷方式电路或可旁路部分中的一个。

10. 发明授权

EP2024819B1 GRAPHICS PROCESSOR WITH ARITHMETIC AND ELEMENTARY FUNCTION UNITS 有权转让
标题翻译：算术和基本功能单元图形处理器
公开(公告)号：EP2024819B1
公开(公告)日：2012-06-06
申请号：EP07797797.3
申请日：2007-05-25
申请人： Qualcomm Incorporated
发明人： BOURD, Alexei, V. , DU, Yun , YU, Chun , JIAO, Guofang
IPC分类号： G06F9/38 , G06T1/20
CPC分类号： G06T1/20 , G06F9/30167 , G06F9/383 , G06F9/3851 , G06F9/3885
摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.

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