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1. 发明公开

EP4007160A1 CRYSTAL OSCILLATOR START-UP CIRCUIT AND METHOD 审中-实审
公开(公告)号：EP4007160A1
公开(公告)日：2022-06-01
申请号：EP20210648.0
申请日：2020-11-30
申请人： NXP B.V.
发明人： Verlinden, Jos , Ahmed, Rehan , Hoogendoorn, Reinier
IPC分类号： H03B5/06 , H03B5/36
摘要： A circuit and method for starting-up a crystal oscillator is described. A crystal resonator is configured to be coupled to a start-up circuit including an H-bridge circuit having a number of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of the motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator in a first polarity during a first switch control phase and a second opposite polarity during a second switch control phase. During a respective first subphase of the respective switch control phase, the plurality of switches are configured in a first configuration to couple the supply node to a respective crystal resonator terminal. During a respective second subphase of the respective switch control phase the plurality of switches are configured in a second configuration to couple the supply node to the respective crystal resonator terminal. The resistance between the supply node and the respective crystal resonator terminal is larger in the second configuration than the first configuration. A zero-crossing is detected during each respective second sub-phase.

2. 发明授权

EP2736167B1 Amplifier with filtering 有权
公开(公告)号：EP2736167B1
公开(公告)日：2019-08-28
申请号：EP13194181.7
申请日：2013-11-25
申请人： NXP B.V.
发明人： Verlinden, Jos , van de Beek, Remco , Ciacci, Massimo
IPC分类号： H03F3/00 , H03F3/189 , H03F3/21 , H03F3/217 , H03F3/24 , H03M1/66

3. 发明公开

EP2680519A1 Pre-equalizer for a digitally modulated RF signal and method 有权
标题翻译： Vorentzerrerfürein digital moduliertes HF-Signal und Verfahren
公开(公告)号：EP2680519A1
公开(公告)日：2014-01-01
申请号：EP12174076.5
申请日：2012-06-28
申请人： NXP B.V.
发明人： Van de Beek, Remco , Ciacci, Massimo , Verlinden, Jos , Al-Kadi, Ghiath
IPC分类号： H04L25/03 , H04L27/36 , H03F1/32
CPC分类号： H04L25/03891 , H03F1/3241 , H03F3/195 , H03F3/24 , H04L25/03343 , H04L25/49 , H04L27/368
摘要： A method for pre-equalizing a digital modulated RF signal is presented. The method comprises receiving an input stream of symbols (x(i)) representing a phase change and magnitude of an RF signal, the magnitudes of the symbols in the input stream are constant, the phase changes of the symbols in the input stream encode digital information, and adjusting the input stream of symbols to reduce inter-symbol interference in transmission of an RF signal modulated according to the input stream, thus obtaining an equalized stream of symbols (x'(i)), each symbol of the equalized stream representing a phase change and magnitude of an RF signal. The adjusting comprising iteratively determining a next symbol of the equalized stream (x'(n)) after receiving a next symbol of the input stream (x(n)) by multiplying said next symbol of the input stream (x(n)) with a next adjusting real number (a(n)),
multiplying a previous symbol of the input stream (x(n-1)) with a previous adjusting real number (a(n-1)), said previous symbol being received directly before said next symbol of the input stream, and computing the next symbol of the equalized stream from the multiplied next symbol of the input stream and the multiplied previous symbol of the input stream.
摘要翻译：提出了一种用于预均衡数字调制RF信号的方法。该方法包括接收表示RF信号的相位变化和幅度的符号（x（i））的输入流，输入流中符号的大小是恒定的，输入流中符号的相位变化将数字信息，并且调整符号的输入流以减少根据输入流调制的RF信号的传输中的符号间干扰，从而获得均衡的符号流（x'（i）），所述均衡流的每个符号表示 RF信号的相位变化和幅度。所述调整包括通过将所述输入流（x（n））的所述下一个符号与所述输入流（x（n））的所述下一符号相乘而将所述输入流（x（n））的下一个符号与下一个调整实数（a（n）），将输入流（x（n-1））的先前符号与先前调整实数（a（n-1））相乘），所述先前符号直接在表示输入流的下一个符号，并从输入流的相乘的下一个符号和输入流的相乘的先前符号计算均衡流的下一个符号。

4. 发明公开

EP2843840A1 Clock synchronizer for aligning remote devices 有权
标题翻译： Taktsynchronisiereinrichtung zum Ausrichten von Fernvorrichtungen
公开(公告)号：EP2843840A1
公开(公告)日：2015-03-04
申请号：EP14176889.5
申请日：2014-07-14
申请人： NXP B.V.
发明人： Verlinden, Jos , van de Beek, Remco Cornelis Herman
IPC分类号： H03L7/099 , H03L7/14 , H03L7/23
摘要： Various aspects of the present disclosure are directed apparatuses and methods including a first phase locked loop (PLL) circuit and a second PLL circuit. The first PLL circuit receives a carrier signal that is transmitted over a communications channel from a non-synchronous device, and generates a PLL-PLL control signal. The second PLL circuit receives a stable reference-oscillation signal, and, in response to the PLL-PLL control signal indicating a frequency offset, adjusts a fractional divider ratio of the second PLL circuit. The first PLL circuit and the second PLL circuit are configured to produce an output frequency signal that is synchronous to the carrier signal.
摘要翻译：本公开的各个方面涉及包括第一锁相环（PLL）电路和第二PLL电路的装置和方法。第一PLL电路从非同步装置接收通过通信信道发送的载波信号，并产生PLL-PLL控制信号。第二PLL电路接收稳定的基准振荡信号，响应于表示频率偏移的PLL-PLL控制信号，调整第二PLL电路的分数除数比。第一PLL电路和第二PLL电路被配置为产生与载波信号同步的输出频率信号。

5. 发明授权

EP2680519B1 Pre-equalizer for a digitally modulated RF signal and method 有权
标题翻译：预均衡器对数字调制的RF信号和方法
公开(公告)号：EP2680519B1
公开(公告)日：2014-08-20
申请号：EP12174076.5
申请日：2012-06-28
申请人： NXP B.V.
发明人： Van de Beek, Remco , Ciacci, Massimo , Verlinden, Jos , Al-Kadi, Ghiath
IPC分类号： H04L25/03 , H04L27/36 , H03F1/32
CPC分类号： H04L25/03891 , H03F1/3241 , H03F3/195 , H03F3/24 , H04L25/03343 , H04L25/49 , H04L27/368

6. 发明公开

EP4174462A1 TEMPERATURE SENSOR 审中-实审
公开(公告)号：EP4174462A1
公开(公告)日：2023-05-03
申请号：EP21205827.5
申请日：2021-11-01
申请人： NXP B.V.
发明人： Delke, Alexander Sebastian , Annema, Anne Johan , Verlinden, Jos , Nauta, Bram , Jordens, Mike
IPC分类号： G01K7/01
摘要： A temperature sensor and method of temperature sensing is described. A first reference current is provided to a dual-slope ADC during a first slope time duration of a dual-slope ADC conversion cycle. A second reference current is provided to the dual-slope ADC during a second slope time duration of the dual-slope ADC conversion cycle. A digital codeword corresponding to a ratio of the first and second reference currents is then output by the dual-slope ADC. The first and second reference current ratio is related to the temperature.

7. 发明授权

EP3086478B1 WIRELESS RECEIVER AND METHOD 有权
公开(公告)号：EP3086478B1
公开(公告)日：2018-09-19
申请号：EP15164932.4
申请日：2015-04-23
申请人： NXP B.V.
发明人： van de Beek, Remco , Verlinden, Jos
IPC分类号： H04B1/40 , H04L27/06
CPC分类号： H04B1/12 , H04B1/40 , H04L27/06 , H04L27/066
摘要： A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analogue-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.

8. 发明公开

EP3086478A1 WIRELESS RECEIVER AND METHOD 审中-公开
标题翻译： DRAHTLOSEREMPFÄNGERUND VERFAHREN
公开(公告)号：EP3086478A1
公开(公告)日：2016-10-26
申请号：EP15164932.4
申请日：2015-04-23
申请人： NXP B.V.
发明人： van de Beek, Remco , Verlinden, Jos
IPC分类号： H04B1/40 , H04L27/06
CPC分类号： H04B1/12 , H04B1/40 , H04L27/06 , H04L27/066
摘要： A receiver and method for a wireless signal transmission system use digital amplitude modulation of a base band signal having a symbol clock frequency. The receiver includes a reference generator which generates a local reference frequency, a mixer to extract the base band signal, a high pass filter to suppress a DC component, an amplifier, an analogue-to-digital converter and a digital signal processor to receive digital signals and extract symbols. A base band signal rotation detection circuit detects rotation of the base band signal upstream of the high pass filter. The digital signal processor determines a symbol clock phase by generating a coarse estimate of the symbol clock phase and correcting the coarse estimate based on detected rotations of the base band signal. A determination that the symbol clock phase corresponds to a complete rotation is used in relation to the extraction of symbols.
摘要翻译：用于无线信号传输系统的接收机和方法使用具有符号时钟频率的基带信号的数字幅度调制。接收机包括产生本地参考频率的参考发生器，提取基带信号的混频器，抑制DC分量的高通滤波器，放大器，模数转换器和数字信号处理器以接收数字信号和提取符号。基带信号旋转检测电路检测高通滤波器上游的基带信号的旋转。数字信号处理器通过生成符号时钟相位的粗略估计并基于检测到的基带信号的旋转来校正粗略估计来确定符号时钟相位。符号时钟相位对应于完整旋转的确定与符号的提取有关。

9. 发明公开

EP2736167A1 Amplifier with filtering 有权
标题翻译： Verstärkermit Filterung
公开(公告)号：EP2736167A1
公开(公告)日：2014-05-28
申请号：EP13194181.7
申请日：2013-11-25
申请人： NXP B.V.
发明人： Verlinden, Jos , van de Beek, Remco , Ciacci, Massimo
IPC分类号： H03F3/00 , H03F3/189 , H03F3/21 , H03F3/217 , H03F3/24 , H03M1/66
CPC分类号： H03G1/04 , H03F3/005 , H03F3/189 , H03F3/211 , H03F3/2175 , H03F3/245 , H03F3/68 , H03M1/662 , H03M1/804
摘要： Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset an input signal in phase, as presented to respective amplifiers. The phase off set is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain.
摘要翻译：信号被处理以便于缓解和/或消除信号内的不合要求的部件。与一个或多个实施例一致，输入/延迟电路按相应的放大器相同地偏移输入信号。在相应放大器的输出组合时，使用相位偏移来消除信号的不期望的分量。例如，这种方法可以涉及在数字域中的相位偏移，并且在模拟域中呈现的信号的组合进行校正。

10. 发明公开

EP3917005A1 FREQUENCY REFERENCE GENERATOR 有权
公开(公告)号：EP3917005A1
公开(公告)日：2021-12-01
申请号：EP21170793.0
申请日：2021-04-27
申请人： NXP B.V.
发明人： Jin, Yanyu , Verlinden, Jos , Liu, Maoqiang
IPC分类号： H03B5/12 , H03K21/00 , H03L1/00 , H03L5/00 , H03L1/02
摘要： An LC oscillator has a tank driver connected to cause a matched-resistance LC tank to oscillate. The LC tank has an inductor leg in parallel with a capacitor leg. The inductor leg has an explicit inductor having an implicit resistance level R L . The capacitor leg has an explicit capacitor having an implicit resistance level R C connected in series with an explicit resistor having an explicit resistance level R R , where R M = ( R C + R R ) is substantially equal to R L . The LC oscillator may have a non-trimmable LC tank and be part of a temperature-compensated frequency reference generator having standalone frequency adjustment circuitry that offers better than ±0.1% frequency accuracy (after single trim and batch calibration) over process, voltage, and temperature variations, and lifetime, which can serve as a low-cost replacement for a crystal oscillator for many applications.

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