专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明公开

EP1892837A1 Clock supply circuit and clock supply method 审中-公开
标题翻译： Taktversorgungsschaltung und Taktversorgungsverfahren
公开(公告)号：EP1892837A1
公开(公告)日：2008-02-27
申请号：EP07114599.9
申请日：2007-08-20
申请人： NEC CORPORATION
发明人： Kon, Makoto , Okuyama, Keiichi
IPC分类号： H03L7/14
CPC分类号： H03L7/143 , H03L7/145 , H03L7/146
摘要： The present invention provides a clock supply device and a clock supply method by which the holdover characteristics that maintains with high precision the same frequency as the frequency observed immediately before an error can be achieved simply with the addition of a high stability oscillator. An output clock signal that is output from a conventional PLL circuit is monitored with a clock signal of a high-stability fixed oscillator, and the monitor result is written in a memory. A holdover reference generating circuit averages the result written over a certain period of time. When a frequency error monitoring circuit detects a frequency error in an input reference signal, a selector selects a holdover reference, instead of the input reference signal, and inputs the holdover reference to the PLL circuit. Alternatively, the holdover reference generating circuit may select the input of the PLL circuit at the time of an error, and then perform holdover.
摘要翻译：本发明提供一种时钟提供装置和时钟提供方法，通过该时钟供给装置和时钟提供方法，可以简单地通过添加高稳定性振荡器来实现保持与高精度保持相同频率的保持特性。由常规PLL电路输出的输出时钟信号由高稳定性固定振荡器的时钟信号监视，监视结果写入存储器。保持参考产生电路对在一段时间内写入的结果进行平均。当频率误差监视电路检测到输入参考信号中的频率误差时，选择器选择保持参考而不是输入参考信号，并将保持参考输入到PLL电路。或者，保持参考生成电路可以在错误时选择PLL电路的输入，然后执行保持。

IPRDB

热门服务

关于我们

友情链接

联系方式