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1. 发明公开

EP2719082A1 MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER 有权
标题翻译：修改的动态元件匹配用于在管道中的模拟数字转换器减少延迟
公开(公告)号：EP2719082A1
公开(公告)日：2014-04-16
申请号：EP12731226.2
申请日：2012-06-07
申请人： Microchip Technology Incorporated
发明人： MEACHAM, Daniel , PANIGADA, Andrea , GRILO, Jorge
IPC分类号： H03M1/06
CPC分类号： H03M1/0673 , H03M1/0641 , H03M1/164
摘要： A pipeline ADC is provided in which a DEM function and summation of sequences occur within a flash ADC. According to various aspects of the present disclosure, embedding the processing functions needed for DAC and amplifier error correction with the circuitry of a coarse ADC and rearranging the digital calibration blocks HDC and DNC ensures accurate estimation of the errors.

2. 发明公开

EP2719078A1 DISTRIBUTED BOOTSTRAP SWITCH 有权
标题翻译：分布式举开关
公开(公告)号：EP2719078A1
公开(公告)日：2014-04-16
申请号：EP12727553.5
申请日：2012-06-07
申请人： Microchip Technology Incorporated
发明人： GRILO, Jorge , MEACHAM, Daniel , PANIGADA, Andrea
IPC分类号： H03K17/06
CPC分类号： H03K17/063 , H03K17/04123 , H03K2217/0054
摘要： An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch for connecting electrical power to a first terminal of at least one capacitor; at least one second switch for connecting a second terminal of the at least one capacitor to a signal to be sampled; at least one third switch for connecting the first terminal of the at least one capacitor to the control gate of at least one sampling network input switch; at least one fourth switch for connecting the at least one sampling network input switch to a substrate; and at least one fifth switch for connecting the second terminal of the at least one capacitor to the substrate.

3. 发明授权

EP3044796B1 SAMPLING INPUT STAGE WITH MULTIPLE CHANNELS 有权
标题翻译：用多个通道采样输入级
公开(公告)号：EP3044796B1
公开(公告)日：2017-11-01
申请号：EP14776934.3
申请日：2014-09-09
申请人： Microchip Technology Incorporated
发明人： MEACHAM, Daniel, R. , PANIGADA, Andrea , SHIH, David
IPC分类号： G11C27/02 , H03M1/06 , H03M1/10 , H03M1/12 , H03M1/16
CPC分类号： H03M1/08 , G11C27/02 , G11C27/024 , H03M1/066 , H03M1/1033 , H03M1/12 , H03M1/1205 , H03M1/122 , H03M1/1225 , H03M1/167 , H03M1/36

4. 发明授权

EP2719081B1 MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER 有权
标题翻译：改进的动态元素匹配减少流水线模拟到数字转换器的延迟
公开(公告)号：EP2719081B1
公开(公告)日：2017-08-09
申请号：EP12731225.4
申请日：2012-06-07
申请人： Microchip Technology Incorporated
发明人： MEACHAM, Daniel , PANIGADA, Andrea , GRILO, Jorge
IPC分类号： H03M1/06 , H03M1/16
CPC分类号： H03M1/0673 , H03M1/0641 , H03M1/164

5. 发明公开

EP2719080A1 MULTICHANNEL ANALOG TO DIGITAL CONVERTER APPARATUS AND METHOD FOR USING 无效
标题翻译：多路模拟 - 数字转换器和使用方法
公开(公告)号：EP2719080A1
公开(公告)日：2014-04-16
申请号：EP12730712.2
申请日：2012-06-07
申请人： Microchip Technology Incorporated
发明人： PANIGADA, Andrea , GRILO, Jorge , MEACHAM, Daniel
IPC分类号： H03M1/06
CPC分类号： H03M1/0626 , H03M1/1225
摘要： A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.

6. 发明公开

EP3044796A1 SAMPLING INPUT STAGE WITH MULTIPLE CHANNELS 有权
标题翻译： ABTASTUNGSEINGANGSSTUFE MIT MEHRERENKANÄLEN
公开(公告)号：EP3044796A1
公开(公告)日：2016-07-20
申请号：EP14776934.3
申请日：2014-09-09
申请人： Microchip Technology Incorporated
发明人： MEACHAM, Daniel, R. , PANIGADA, Andrea , SHIH, David
IPC分类号： G11C27/02 , H03M1/12 , H03M1/06
CPC分类号： H03M1/08 , G11C27/02 , G11C27/024 , H03M1/066 , H03M1/1033 , H03M1/12 , H03M1/1205 , H03M1/122 , H03M1/1225 , H03M1/167 , H03M1/36
摘要： An analog input stage has m differential input channels, wherein m>l. The analog input stage is configured to select one of the m differential input channels and provide an output signal. The analog input stage has n identical selection units each having m differential channel inputs and one differential output, wherein n is at least 2111"1. Each selection unit is operable to be coupled to any of the differential input channels through respective differential multiplexer units, wherein the multiplexor units are driven to select one of the differential input channels and couple the selected differential channel input through a butterfly switch unit with the differential output of the selection unit. The differential output signals of the n selection units are combined whereby unwanted crosstalk from channels other than a selected channel are removed by cancellation.
摘要翻译：模拟输入级具有m个差分输入通道，其中m> 1。模拟输入级被配置为选择m个差分输入通道之一并提供输出信号。模拟输入级具有n个相同的选择单元，每个具有m个差分通道输入和一个差分输出，其中n至少为2m-1。每个选择单元可操作以通过相应的差分多路复用器单元耦合到任何差分输入通道，其中多路复用器单元被驱动以选择差分输入通道中的一个，并通过蝶形开关单元将所选择的差分通道输入与差分输出选择单元。组合n个选择单元的差分输出信号，从而通过取消消除了除了所选频道之外的信道的不希望的串扰。

7. 发明公开

EP2719081A1 MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER 有权
标题翻译：修改的动态元件匹配用于在管道中的模拟数字转换器减少延迟
公开(公告)号：EP2719081A1
公开(公告)日：2014-04-16
申请号：EP12731225.4
申请日：2012-06-07
申请人： Microchip Technology Incorporated
发明人： MEACHAM, Daniel , PANIGADA, Andrea , GRILO, Jorge
IPC分类号： H03M1/06
CPC分类号： H03M1/0673 , H03M1/0641 , H03M1/164
摘要： A circuit in an analog-to-digital converter, ADC, includes an amplifier (520) configured to receive an output of a backend ADC (512); a harmonic distortion correction circuit, HDC (522), coupled to the amplifier (520) and configured to correct distortion components due to the residue amplifier (506) present in a digital signal from the back-end ADC (512), the HDC circuit (522) providing an output to an adder (530), the adder (530) receiving a coarse digital output from a coarse ADC (502); and a DAC noise cancellation circuit, DNC (526), configured to provide an output to the adder (530), wherein the DNC circuit (526) is configured to correct distortion components due to the DAC (504) present in the digital signal from the backend ADC (512); wherein the output of the adder (530) is an ADC digital output and wherein the ADC digital output forms an input (523) to the HDC and the DNC.
摘要翻译：在模拟到数字转换器（ADC）包括配置为接收至少一个后端DAC的输出放大器的电路; 谐波失真校正电路（HDC）耦合到所述放大器，并且被配置来校正失真分量由于存在于从后端ADC的数字信号残余放大器中，HDC电路在输出端提供对在加法器中，加法器接收一个粗数字输出从粗ADC; 和DAC噪声消除电路（DNC）被配置为提供到输出到加法器，worin的DNC电路被配置为校正由于DAC存在于从后端ADC的数字信号中的失真分量; worin加法器的输出是一个ADC数字输出和worin输入到HDC和DNC的ADC数字输出的形式。

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