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1. 发明公开

EP3070849A1 SUCCESSIVE APROXIMATION REGISTER ANALOG TO DIGITAL CONVERTERS 审中-公开
标题翻译：模拟数字服务器麻省理工学院NÄHERUNGSREGISTER
公开(公告)号：EP3070849A1
公开(公告)日：2016-09-21
申请号：EP15170086.1
申请日：2015-06-01
申请人： MediaTek, Inc
发明人： Lee, Zwei-Mei , Liu, Chun-Cheng
IPC分类号： H03M1/46 , H03M1/10 , H03M1/06
CPC分类号： H03M1/468 , H03M1/0641 , H03M1/1004 , H03M1/1009 , H03M1/38 , H03M1/40 , H03M1/403
摘要： A successive approximation register,SAR, analog to digital converter, ADC, circuit receiving an analog input signal (Vin) and operating in a sample phase and a conversion phase following the sample phase to generate a digital output signal (D 0 ) , comprising:
a plurality of capacitors(C 0 , ..., C N-1 ) coupled to a summing node (N20), wherein before the conversion phase, a target capacitor (C j ) among the plurality of capacitors is coupled to a direct current voltage (q*VR) and the other capacitors among the plurality of capacitors are coupled to the analog input signal;
a comparator (20) having an input terminal coupled to the summing node, wherein in the conversion phase, the comparator performs a comparison operation to a summing voltage at the summing node; and
a logic unit (21) having a plurality of weighting values corresponding to the plurality of capacitors respectively and generating the digital output signal according to the weighting values and a comparison result of the comparison operation,
wherein the DC voltage has a first voltage level or a second voltage level different from the first voltage level according to a random sequence (q),
an extraction and compensation unit (11,110) receiving the digital output signal,
wherein the extraction and compensation unit performs a correlation operation (40) to the digital output signal with the random sequence and further performs a low-pass-filtering operation(41) to the digital output signal to generate a calibrated weighting value (Wj), and
wherein the extraction and compensation unit corrects the digital output signal based on the weighting value of the target capacitor and
wherein the weighting value of the target capacitor is calibrated according to the digital output signal and the random sequence.
摘要翻译：一个逐次逼近寄存器SAR，模数转换器，ADC，接收模拟输入信号（Vin）的电路，并在采样相位后跟在采样相位之后的转换阶段工作以产生数字输出信号（D 0），包括：耦合到求和节点（N20）的多个电容器（C 0，...，C N-1），其中在转换阶段之前，多个电容器中的目标电容器（C j）被耦合到直流电多个电容器中的电压（q * VR）和其他电容器耦合到模拟输入信号; 比较器（20），其具有耦合到所述求和节点的输入端，其中在所述转换阶段中，所述比较器对所述求和节点的求和电压进行比较运算; 和具有与多个电容器对应的多个加权值的逻辑单元（21），并且根据加权值和比较运算的比较结果产生数字输出信号，其中直流电压具有第一电压电平或根据随机序列（q）与第一电压电平不同的第二电压电平，接收数字输出信号的提取和补偿单元（11,110），其中提取和补偿单元对数字输出执行相关操作（40）信号，并且进一步对数字输出信号执行低通滤波操作（41）以产生校准加权值（Wj），并且其中提取和补偿单元根据加权值对数字输出信号进行校正的目标电容器，并且其中根据数字输出信号和th校准目标电容器的加权值 e随机序列。

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