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1. 发明公开

EP0974912A2 Fault resilient/fault tolerant computing 失效
标题翻译： Fehler-betriebssichere / Fehler tolerante Computerbetriebsmethode
公开(公告)号：EP0974912A2
公开(公告)日：2000-01-26
申请号：EP99122245.6
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F15/16 , G06F11/00 , G06F13/00 , G06F15/76
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).
摘要翻译：一种同步至少两个计算元件（CE1，CE2）的方法，每个计算元件（CE1，CE2）具有与其他计算元件的时钟异步工作的时钟，包括从一组信号中选择一个或多个指定为元时间信号的信号，计算元件（CE1，CE2），监视计算元件（CE1，CE2），以通过计算元件（CE1）之一检测所选信号的产生，等待其他计算元件（CE2）产生所选择的信号，向每个计算元件发送等价的时间更新，以及基于时间更新来更新计算元件（CE1，CE2）的时钟。在本发明的第二方面中，通过将第一处理器指定为计算元件（204），指定作为控制器的第二处理器（202）来产生故障恢复或容忍的计算机（200），连接所述计算元件（204 ）和控制器（202）以产生模块对，并且连接至少两个模块对以产生故障回复或容错计算机（200）。计算机（200）的每个计算元件（202,204）以与其它计算元件（202,204）相同的周期数执行所有指令。计算机系统包括一个或多个控制器（202）和至少两个计算元件（204）。

2. 发明授权

EP0986008B1 Computer system comprising controllers and computing elements 失效
标题翻译：一种计算机系统，具有控制单元和计算机元件
公开(公告)号：EP0986008B1
公开(公告)日：2008-04-16
申请号：EP99122243.1
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F15/16 , G06F11/16 , G06F15/76 , G06F13/00 , G06F11/00
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

3. 发明公开

EP0986008A3 Computer system comprising controllers and computing elements 失效
标题翻译：一种计算机系统，具有控制单元和计算机元件
公开(公告)号：EP0986008A3
公开(公告)日：2000-07-19
申请号：EP99122243.1
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F15/16 , G06F11/16 , G06F15/76 , G06F13/00 , G06F11/00
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

4. 发明授权

EP0974912B1 Fault resilient/fault tolerant computing 失效
标题翻译：可靠的错误/容错计算机操作方法
公开(公告)号：EP0974912B1
公开(公告)日：2008-11-05
申请号：EP99122245.6
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F11/07 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

5. 发明公开

EP0986007A3 Method of isolating I/O requests 失效
标题翻译：用于I / O请求的隔离工艺
公开(公告)号：EP0986007A3
公开(公告)日：2001-11-07
申请号：EP99122244.9
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F13/10 , G06F13/38
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of isolating I/O requests from computing operations in a computer, comprising the steps of: providing a virtual I/O unit that simulates the interface of a physical I/O device; intercepting an I/O request by a computing element that is addressed to the physical I/O device; providing the intercepted I/O request to the virtual I/O unit; transmitting the contents of the virtual I/O unit to an I/O processor; and at the I/O processor, providing the transmitted contents of the virtual I/O device to the physical I/O device.

6. 发明公开

EP0974912A3 Fault resilient/fault tolerant computing 失效
标题翻译：可靠的错误/容错计算机操作方法
公开(公告)号：EP0974912A3
公开(公告)日：2000-07-19
申请号：EP99122245.6
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F11/07 , G06F11/16 , G06F11/00
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

7. 发明公开

EP0986008A2 Computer system comprising controllers and computing elements 失效
标题翻译：一种计算机系统，具有控制单元和计算机元件
公开(公告)号：EP0986008A2
公开(公告)日：2000-03-15
申请号：EP99122243.1
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F15/16 , G06F11/16 , G06F15/76 , G06F13/00
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

8. 发明公开

EP0986007A2 Method of isolating I/O requests 失效
标题翻译：用于I / O请求的隔离工艺
公开(公告)号：EP0986007A2
公开(公告)日：2000-03-15
申请号：EP99122244.9
申请日：1994-11-15
申请人： MARATHON TECHNOLOGIES CORPORATION
发明人： Bissett, Thomas D. , McCollum, James D. , Glorioso, Robert M. , Tremblay, Glenn A. , Troiani, Mario , Fiorentino, Richard D. , McCauley, Diane T.
IPC分类号： G06F13/10
CPC分类号： G06F11/1658 , G06F1/14 , G06F11/1641 , G06F11/1645 , G06F11/1683 , G06F11/1687 , G06F11/1691 , G06F11/181 , G06F11/185 , G06F11/2005 , G06F11/2017
摘要： A method of synchronizing at least two computing elements (CE1, CE2) that each have clocks that operate asynchronously of the clocks of the other computing elements includes selecting one or more signals, designated as meta time signals, from a set of signals produced by the computing elements (CE1, CE2), monitoring the computing elements (CE1, CE2) to detect the production of a selected signal by one of the computing elements (CE1), waiting for the other computing elements (CE2) to produce a selected signal, transmitting equally valued time updates to each of the computing elements, and updating the clocks of the computing elements (CE1, CE2) based on the time updates. In a second aspect of the invention, fault resilient, or tolerant, computers (200) are produced by designating a first processor as a computing element (204), designating a second processor (202) as a controller, connecting the computing element (204) and the controller (202) to produce a modular pair, and connecting at least two modular pairs to produce a fault resilient or fault tolerant computer (200). Each computing element (202, 204) of the computer (200) performs all instructions in the same number of cycles as the other computing elements (202, 204). The computer systems include one or more controllers (202) and at least two computing elements (204).

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