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1. 发明公开

EP3201774A1 VERTEILTES ECHTZEITCOMPUTERSYSTEM UND ZEITGESTEUERTE VERTEILEREINHEIT 有权转让
公开(公告)号：EP3201774A1
公开(公告)日：2017-08-09
申请号：EP15781854.3
申请日：2015-09-28
申请人： FTS Computertechnik GmbH
发明人： POLEDNA, Stefan , KOPETZ, Hermann
IPC分类号： G06F11/07
CPC分类号： G06F11/0796 , G06F11/1645 , G06F11/165 , G06F11/185 , G06F2201/805
摘要： The invention relates to a time-controlled distribution unit (30, 31) for the distribution of messages in a distributed computer system for safety-critical applications. Said distribution unit is designed as a self-testing functional unit and comprises input channels (201
… 222) for receiving time-controlled periodic input messages from node computers (20, 21, 22) upstream in the data flow, and output channels (301
… 313) for transmitting time-controlled periodic output messages to the node computers (50, 51, 52) downstream in the data flow, a comparator (40) being provided in the distribution unit and being designed to analyze, by means of a "simple" software, useful information contained in the input messages, and to decide whether output messages are output and, if so, which useful information is contained in the output messages.
摘要翻译：本发明涉及一种用于在分布式计算机系统中分发消息以用于安全关键型应用的时间控制分配单元（30,31）。所述分配单元被设计为自测试功能单元并且包括用于接收来自数据流中上游的节点计算机（20,21,22）的时间控制的周期性输入消息的输入通道（201 ... 222），以及输出通道（301 ... 313），用于将时间控制的周期性输出消息传送到数据流中下游的节点计算机（50,51,52），比较器（40）被提供在分配单元中，并被设计为借助于“ 简单的“软件，包含在输入消息中的有用信息，并决定是否输出输出消息，如果是，输出消息中包含哪些有用的信息。

2. 发明授权

EP2958022B1 INHERENT FAIL SAFE ENABLING CONTROL AND COMMAND UNIT WITH TWO OUT OF TWO ARCHITECTURE 有权转让
标题翻译：固有的故障故障单元与2关2架构，火力与指挥激活
公开(公告)号：EP2958022B1
公开(公告)日：2017-02-01
申请号：EP15175307.6
申请日：2013-04-24
申请人： ALSTOM Transport Technologies
发明人： Bachetti, Vittorio , Motta, Sara , Campedelli, Francesco
IPC分类号： G06F11/07 , G06F11/16 , G06F11/18
CPC分类号： G06F11/1645

3. 发明公开

EP2423818A4 ASYNCHRONOUS REMOTE COPY SYSTEM AND STORAGE CONTROL METHOD 失效
标题翻译：异步远程复制系统和存储控制方法
公开(公告)号：EP2423818A4
公开(公告)日：2014-04-30
申请号：EP10841823
申请日：2010-04-07
申请人： HITACHI LTD
发明人： KONDO SHUJI , OKUMOTO KATSUHIRO
IPC分类号： G06F11/20 , G06F11/14
CPC分类号： G06F11/1645 , G06F11/1456 , G06F11/2058 , G06F11/2074 , G06F11/2079 , G06F11/2082 , G06F2201/855
摘要： If the first storage apparatus is suspended, it is determined which of the update number which the journal recently reflected in the second storage apparatus comprises and the update number which the journal recently reflected in the third storage apparatus comprises is the newer. It is determined, in the newer storage apparatus which is determined to comprise the newer update number, whether one or more differential journals from the journal comprising the update number next to the update number which is not determined to be the newer to the journal comprising the update number determined to be the newer exist or not. If the result of the determination is positive, from the newer storage apparatus to the previous storage apparatus which is not the newer of the second and the third storage apparatuses, one or more differential JNLs are copied. In the previous storage apparatus, one or more differential JNLs are reflected in order of the update numbers, to the data volumes in the previous storage apparatus.

4. 发明公开

EP1675004A3 Fault tolerant system and controller, access control method, and control program used in the fault tolerant system 审中-公开
标题翻译：一个容错系统和控制器，访问控制方法和控制程序在容错系统中使用
公开(公告)号：EP1675004A3
公开(公告)日：2010-09-01
申请号：EP05027907.4
申请日：2005-12-20
申请人： NEC Corporation
发明人： Mizutani, Fumitoshi
IPC分类号： G06F11/16
CPC分类号： G06F11/1645 , G06F11/165 , G06F11/1683
摘要： The present invention has been made to realize access processing performed in accordance with synchronous/asynchronous state between processors in a fault tolerant system. In two systems that constitute a fault tolerant system, a router assigns, to an access packet transmitted from a CPU to an 10 device, tag information including ID codes of access source and destination and information indicating whether the access packet is synchronous access. An access comparison section has buffers and that retain the packets from the CPU on a system basis, a tag check section that determines whether each packet is synchronous packet access based on the tag information assigned to the packets retained in the buffers, and a comparison section that outputs the packet from one system to an IO IF and discards the packet from other system in the case where the packet is synchronous access.

5. 发明公开

EP2113842A1 Scaleable self-checking processing platform 审中-公开
标题翻译： Skalierbare，selbstprüfendeVerarbeitungsplattform
公开(公告)号：EP2113842A1
公开(公告)日：2009-11-04
申请号：EP09158290.8
申请日：2009-04-20
申请人： Honeywell International Inc.
发明人： Birkedahl, Byron , Wilt, Nicholas , McCready, Art , Hall, Brendan , Larson, Aaron
IPC分类号： G06F11/16 , G06F9/48
CPC分类号： G06F9/4881 , G06F11/1645 , G06F11/1687
摘要： Methods and systems for a scalable self-checking processing platform are described herein. According to one embodiment, during an execution frame, a first processing element executes both a high-criticality application and a first low-criticality application. During that same execution frame, a second processing element executes both the high-criticality application and a second low-criticality application. The high-criticality application output from the first processing element is compared with that from the second processing element before the next execution frame, and a fault occurs when the output does not match. The low-criticality application is not duplicated or compared. This and other embodiments allow high-criticality applications to be appropriated checked while avoiding the over-dedication of resources to low-criticality applications that do not warrant self-checking.
摘要翻译：本文描述了可扩展自检处理平台的方法和系统。根据一个实施例，在执行帧期间，第一处理元件执行高关键性应用和第一低关键性应用。在该相同的执行帧期间，第二处理元件执行高关键性应用和第二低关键性应用。从第一处理单元输出的高临界性应用与下一个执行帧之前的第二处理单元进行比较，当输出不匹配时发生故障。低重要性应用程序不重复或比较。这个和其它实施例允许高度重要性的应用被检查，同时避免资源过度地投入到不保证自我检查的低关键性应用中。

6. 发明公开

EP0752656A3 Fail-fast, fail-functional, fault-tolerant multiprocessor system 失效
标题翻译：快速失败，功能流产容错多系统
公开(公告)号：EP0752656A3
公开(公告)日：1999-08-11
申请号：EP96304199.1
申请日：1996-06-06
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Horst, Robert W.
IPC分类号： G06F11/16
CPC分类号： G01R31/31727 , G01R31/318533 , G06F1/12 , G06F11/004 , G06F11/10 , G06F11/1044 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/167 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F12/0815 , G06F12/1483 , G06F2201/845 , H04L12/56 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

7. 发明公开

EP0748079A3 Communication path verification in a fail-fast, fail-functional, fault-tolerant multiprocessor system 失效
标题翻译：传输路径验证的快速失败，丢失的功能，容错多系统
公开(公告)号：EP0748079A3
公开(公告)日：1999-07-07
申请号：EP96304215.5
申请日：1996-06-06
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Watson, William Joel , Baker, William Edward , Bruckert, William F. , Bunton, William Patterson
IPC分类号： H04L12/26 , G06F11/00
CPC分类号： G01R31/31727 , G01R31/318533 , G06F1/12 , G06F11/004 , G06F11/10 , G06F11/1044 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/167 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F12/0815 , G06F12/1483 , G06F2201/845 , H04L12/56 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.

8. 发明公开

EP0843853A1 MICROPROZESSORSYSTEM FÜR SICHERHEITSKRITISCHE REGELUNGEN 无效
标题翻译：微处理器系统安全关键系统
公开(公告)号：EP0843853A1
公开(公告)日：1998-05-27
申请号：EP96922870.0
申请日：1996-06-20
申请人： ITT Automotive Europe GmbH
发明人： GIERS, Bernhard
IPC分类号： F02D45 , B60T8 , G05B9 , G05B19 , G06F11
CPC分类号： B60T8/885 , B60T2270/413 , G05B9/03 , G05B19/0421 , G05B2219/24182 , G06F11/10 , G06F11/1044 , G06F11/1645
摘要： A microprocessor system for safety-critical regulating systems comprises two synchronously operated central units (1, 2) which receive the same input data and process the same program, ROM (5, 10) and RAM (6, 11) for useful data and verification data and also comparators (18, 19) which check the output signals from the central units (1, 2) and issue shutdown signals if they do not correspond. The central units (1, 2) are connected to the memories and the input/output units via separate bus systems (3, 4) and are coupled by driver stages (15-17) which make it possible for the central units (1, 2) to read and process the data available in both bus systems (3, 4).

9. 发明授权

EP0650615B1 A FAULT-TOLERANT COMPUTER SYSTEM 失效
标题翻译：容错计算机系统。
公开(公告)号：EP0650615B1
公开(公告)日：1998-01-28
申请号：EP93917870.3
申请日：1993-07-19
申请人： SUN MICROSYSTEMS, INC.
发明人： WILLIAMS, Emrys John , LIDDELL, David Charles
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1654 , G06F11/0709 , G06F11/079 , G06F11/10 , G06F11/1415 , G06F11/1604 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/1679 , G06F11/181 , G06F11/185 , G06F11/20
摘要： A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules. Each central processing module contains a means by which the module can compare data on the main data bus with data on a secondary bus within each module in order to determine if there is an inconsistency indicating a hardware fault. If such an inconsistency is detected, each module generates state outputs which reflect the probability that a particular module is the source of the fault. A synchronization bus which is separate from the main data bus interconnects the central processing modules and transmits the state outputs from each module to every other central processing module.

10. 发明公开

EP0757315A2 Fail-fast, fail-functional, fault-tolerant multiprocessor system 失效
标题翻译： Schnellfehlendes，funktionellfehlendes，fehlertolerantes Multiprozessorsystem
公开(公告)号：EP0757315A2
公开(公告)日：1997-02-05
申请号：EP96304175.1
申请日：1996-06-06
申请人： TANDEM COMPUTERS INCORPORATED
发明人： Horst, Robert W. , Garcia, David J. , Bunton, William Patterson , Bruckert, William F. , Fowler, Daniel L. , Jones, Curtis Willard, Jr. , Sonnier, David Paul , Watson, William Joel , Williams, Frank A.
IPC分类号： G06F11/16
CPC分类号： G01R31/31727 , G01R31/318533 , G06F1/12 , G06F11/004 , G06F11/10 , G06F11/1044 , G06F11/1604 , G06F11/1633 , G06F11/1645 , G06F11/165 , G06F11/1658 , G06F11/167 , G06F11/1679 , G06F11/1683 , G06F11/1687 , G06F11/1695 , G06F11/20 , G06F11/2043 , G06F11/2097 , G06F11/2736 , G06F12/0815 , G06F12/1483 , G06F2201/845 , H04L12/56 , H04L47/10 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L69/40
摘要： A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.
Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.
CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
摘要翻译：多处理器系统包括大量相同构造的多个子处理器系统，每个子处理器系统包括中央处理单元（CPU），以及至少一个I / O设备，其通过路由设备互连，该路由设备也互连子处理器系统。任何一个子处理器系统的CPU可以通过路由元件与系统的任何I / O设备或系统的任何CPU通信。 I / O设备和CPU之间的通信是分组消息。来自I / O设备的中断从I / O设备传送到CPU（或从一个CPU到另一个CPU）作为消息数据包。 CPU和I / O设备可以写入或读取系统的CPU的存储器。存储器保护由每个CPU维护的访问验证方法提供，其中CPU和/或I / O设备被提供有对该CPU的存储器的读/写的验证，没有哪个存储器访问被拒绝。

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