专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

EP0131930B1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0131930B1
公开(公告)日：1992-05-20
申请号：EP84108240.7
申请日：1984-07-13
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Isobe, Mitsuo c/o Patent Division , Sakurai, Takayasu c/o Patent Division , Sawada, Kazuhiro c/o Patent Division , Iizuka, Tetsuya c/o Patent Division , Ohtani, Takayuki c/o Patent Division , Aono, Akira
IPC分类号： G06F11/20
CPC分类号： G11C29/84 , G11C29/832
摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells, those memory cells are replaced by redundant memory cells. When defective portions are discovered in the memory cells, the fuse elements corresponding to the memory cells having the defective portions are cut off. Voltages of the select lines connected to the memory cells having the defective portions are held at an L level by the resistors. Due to this, the memory cells having the defective portions are not selected.
摘要翻译：在根据本发明的半导体存储器件中，当在存储器单元中存在缺陷部分时，这些存储器单元被冗余存储器单元替代。当在存储单元中发现缺陷部分时，对应于具有缺陷部分的存储单元的熔丝元件被切断。连接到具有缺陷部分的存储单元的选择线的电压通过电阻保持在L电平。由此，具有缺陷部分的存储器单元未被选择。

2. 发明公开

EP0131930A2 Semiconductor memory device 失效
公开(公告)号：EP0131930A2
公开(公告)日：1985-01-23
申请号：EP84108240.7
申请日：1984-07-13
申请人： KABUSHIKI KAISHA TOSHIBA , Toshiba Micro-Computer Engineering Corporation
发明人： Isobe, Mitsuo c/o Patent Division , Sakurai, Takayasu c/o Patent Division , Sawada, Kazuhiro c/o Patent Division , Iizuka, Tetsuya c/o Patent Division , Ohtani, Takayuki c/o Patent Division , Aono, Akira
IPC分类号： G06F11/20
CPC分类号： G11C29/84 , G11C29/832
摘要： In the semiconductor memory device according to the present invention, when there is a defective portion in the memory cells (7-1 to 7-256), those memory cells are substituted by redundancy memory cells (17-1,17-2). When defective portions were discovered in the memory cells (7-1 to 7-256), the fuse elements (FS-1 to FS-256) corresponding to the memory cells (7-1 to 7-256) having the defective portions are cut off. Voltages of the select lines (5-1 to 5-256) connected to the memory cells having the defective portions are held at L level by the resistors (R-1 to R-256). Due to this, the memory cells (7-1 to 7-256) having the defective portions are not selected.

3. 发明授权

EP0274378B1 Semiconductor memory device 失效
公开(公告)号：EP0274378B1
公开(公告)日：1993-07-07
申请号：EP88100055.8
申请日：1988-01-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsujimoto, Jun-ichi c/o Patent Division , Matsui, Masataka c/o Patent Division , Iwai, Hiroshi c/o Patent Division , Ohtani, Takayuki c/o Patent Division
IPC分类号： G06F11/20
CPC分类号： G11C29/802 , G11C29/844

4. 发明公开

EP0274378A3 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：EP0274378A3
公开(公告)日：1991-11-27
申请号：EP88100055.8
申请日：1988-01-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsujimoto, Jun-ichi c/o Patent Division , Matsui, Masataka c/o Patent Division , Iwai, Hiroshi c/o Patent Division , Ohtani, Takayuki c/o Patent Division
IPC分类号： G06F11/20
CPC分类号： G11C29/802 , G11C29/844
摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder (PD1 - PD4) receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit (SC1 - SC4) receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line of which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.
摘要翻译：在具有普通字线和备用字线的半导体存储器件中，部分解码器（PD1-PD4）接收并解码地址信号的原始逻辑电平的预定两个比特信号，并且该部分解码器互补的逻辑电平，其对应于预定的两个比特信号，并输出预定的两个比特信号和两个对应的比特信号的不同的信号组合。备用字线选择电路（SC1-SC4）接收不同的信号并选择不同的信号中的一个，以便选择与连接有缺陷单元的正常字线相对应的备用字线。部分解码器可以用于正常字线选择和备用字线的选择。利用以这种方式构造的设备，地址信号的位信号不直接输入到备用字线选择电路，而是输入不同位信号组合的信号。备用字线选择电路仅选择不同组合的信号，并且不需要地址信号的部分解码。因此，与常规存储器件相比，布线所需的芯片面积可以显着减小。

5. 发明公开

EP0274378A2 Semiconductor memory device 失效
标题翻译： Halbleiterspeichergerät。
公开(公告)号：EP0274378A2
公开(公告)日：1988-07-13
申请号：EP88100055.8
申请日：1988-01-05
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Tsujimoto, Jun-ichi c/o Patent Division , Matsui, Masataka c/o Patent Division , Iwai, Hiroshi c/o Patent Division , Ohtani, Takayuki c/o Patent Division
IPC分类号： G06F11/20
CPC分类号： G11C29/802 , G11C29/844
摘要： In a semiconductor memory device with normal word lines and spare word lines, a partial decoder (PD1 - PD4) receives and decodes a predetermined two of the bit signals of the original logic levels of an address signal, and two of the bit signals of the complementary logic levels, which correspond to the predetermined two bit signals, and outputs different signal combinations of the predetermined two bit signals and the two corresponding bit signals. A spare word line selecting circuit (SC1 - SC4) receives the different signals and selects one of the different signals in order to select a spare word line which corresponds to a normal word line of which a defective cell is connected. The partial decoder may be used for both the normal word line selection and the selection of spare word lines. With a device constructed in such a manner, bit signals of an address signal are not directly input to the spare word line selecting circuit, but rather signals of different bit signal combinations are input to it. The spare word line selecting circuit merely selects signals of different combinations, and does not need the partial decoding of the address signal. Therefore, the chip area required for wiring may be remarkably reduced when compared with the conventional memory device.
摘要翻译：在具有正常字线和备用字线的半导体存储器件中，部分解码器（PD1-PD4）接收并解码地址信号的原始逻辑电平的预定的两个比特信号，以及两个位信号互补逻辑电平，其对应于预定的两位信号，并输出预定的两位信号和两个对应位信号的不同信号组合。备用字线选择电路（SC1-SC4）接收不同的信号并选择其中一个不同的信号，以便选择与缺陷单元连接的正常字线对应的备用字线。部分解码器可以用于正常字线选择和备用字线的选择。利用以这种方式构造的设备，地址信号的位信号不直接输入到备用字线选择电路，而是输入不同位信号组合的信号。备用字线选择电路仅选择不同组合的信号，并且不需要地址信号的部分解码。因此，与传统的存储器件相比，布线所需的芯片面积可能会显着降低。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式