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1. 发明授权

EP0464666B1 Input-weighted transversal filter 失效
标题翻译：输入加权的横向滤波器
公开(公告)号：EP0464666B1
公开(公告)日：1996-09-11
申请号：EP91110650.8
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA AVE CO., LTD
发明人： Makino, Takashi, c/o Intellectual Property Div. , Goto, Mikio, c/o Intellectual Property Div.
IPC分类号： H03H15/00 , H03H17/06
CPC分类号： H03H17/0225 , H03H17/06

2. 发明公开

EP0464666A3 Input-weighted transversal filter 失效
标题翻译：输入加权横向过滤器
公开(公告)号：EP0464666A3
公开(公告)日：1992-07-29
申请号：EP91110650.8
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA AVE CO., LTD
发明人： Makino, Takashi, c/o Intellectual Property Div. , Goto, Mikio, c/o Intellectual Property Div.
IPC分类号： H03H15/00 , H03H17/06
CPC分类号： H03H17/0225 , H03H17/06
摘要： A selector (44 - 46a) sequentially selects different coefficients during a time interval T. A plurality of coefficient multipliers (41 - 43a) multiply an input signal sampled at intervals T and coefficients selected by the selector. An input circuit (59) converts an input signal supplied at intervals T to a signal of a period of T/2. A pipeline type adder (47 - 49, 50 - 57) adds an output signal of the input circuit and output signals of the coefficient multipliers. An output circuit (63) adds an output signal of the adder in an interval of T/2 and outputs the result of the addition as a signal of a period of T.

3. 发明公开

EP0464666A2 Input-weighted transversal filter 失效
标题翻译：输入加权横向滤波器
公开(公告)号：EP0464666A2
公开(公告)日：1992-01-08
申请号：EP91110650.8
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA , TOSHIBA AVE CO., LTD
发明人： Makino, Takashi, c/o Intellectual Property Div. , Goto, Mikio, c/o Intellectual Property Div.
IPC分类号： H03H15/00 , H03H17/06
CPC分类号： H03H17/0225 , H03H17/06
摘要： A selector (44 - 46a) sequentially selects different coefficients during a time interval T. A plurality of coefficient multipliers (41 - 43a) multiply an input signal sampled at intervals T and coefficients selected by the selector. An input circuit (59) converts an input signal supplied at intervals T to a signal of a period of T/2. A pipeline type adder (47 - 49, 50 - 57) adds an output signal of the input circuit and output signals of the coefficient multipliers. An output circuit (63) adds an output signal of the adder in an interval of T/2 and outputs the result of the addition as a signal of a period of T.
摘要翻译：选择器（44-46a）在时间间隔T期间顺序地选择不同的系数。多个系数乘法器（41-43a）将以间隔T采样的输入信号与由选择器选择的系数相乘。输入电路（59）将以间隔T提供的输入信号转换为周期为T / 2的信号。流水线型加法器（47-49,50-57）将输入电路的输出信号和系数乘法器的输出信号相加。输出电路（63）以T / 2的间隔相加加法器的输出信号，并将相加结果作为周期为T的信号输出。

4. 发明授权

EP0464678B1 Input-weighted transversal filter 失效
标题翻译：输入加权横向滤波器
公开(公告)号：EP0464678B1
公开(公告)日：1996-09-11
申请号：EP91110670.6
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Makino, Takashi, c/o Intellectual Property Div.
IPC分类号： H03H15/00 , H03H17/06 , H03H17/02
CPC分类号： H03H17/06

5. 发明公开

EP0464678A3 Input-weighted transversal filter 失效
公开(公告)号：EP0464678A3
公开(公告)日：1992-07-29
申请号：EP91110670.6
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Makino, Takashi, c/o Intellectual Property Div.
IPC分类号： H03H15/00 , H03H17/06 , H03H17/02
CPC分类号： H03H17/06
摘要： Tap arithmetic units (50) and first delay circuits are arranged alternately. Each of the tap arithmetic units (50) comprises a full-adder array (50a) for multiplying an input signal which has been sampled at regular intervals and coefficients, a second pipeline delay circuit (50b) for delaying outputs of the full-adder array (50a) by a predetermined time and an adder circuit (50c) for adding outputs of the second delay circuit (50b). The first and second delay circuits (50b) are timed to the preceding tap arithmetic unit for arithmetic operations. The use of the second delay circuit (50b) for the timing of arithmetic operations permits the arrangement of the first delay circuit to be simplified.

6. 发明公开

EP0464678A2 Input-weighted transversal filter 失效
标题翻译：输入加权横向滤波器
公开(公告)号：EP0464678A2
公开(公告)日：1992-01-08
申请号：EP91110670.6
申请日：1991-06-27
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Makino, Takashi, c/o Intellectual Property Div.
IPC分类号： H03H15/00 , H03H17/06 , H03H17/02
CPC分类号： H03H17/06
摘要： Tap arithmetic units (50) and first delay circuits are arranged alternately. Each of the tap arithmetic units (50) comprises a full-adder array (50a) for multiplying an input signal which has been sampled at regular intervals and coefficients, a second pipeline delay circuit (50b) for delaying outputs of the full-adder array (50a) by a predetermined time and an adder circuit (50c) for adding outputs of the second delay circuit (50b). The first and second delay circuits (50b) are timed to the preceding tap arithmetic unit for arithmetic operations. The use of the second delay circuit (50b) for the timing of arithmetic operations permits the arrangement of the first delay circuit to be simplified.
摘要翻译：分接算术单元（50）和第一延迟电路交替排列。每个抽头算术单元（50）包括一个全加器阵列（50a），用于将以规则间隔抽样的输入信号和系数相乘;第二流水线延迟电路（50b），用于延迟全加器阵列（50a）延迟预定的时间，加法器电路（50c）用于将第二延迟电路（50b）的输出相加。第一和第二延迟电路（50b）被定时到前一个分
支算术单元进行算术运算。将第二延迟电路（50b）用于算术运算的定时允许简化第一延迟电路的设置。

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