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1. 发明公开

EP0126247A2 Computer system 失效
标题翻译： Rechnersystem。
公开(公告)号：EP0126247A2
公开(公告)日：1984-11-28
申请号：EP84103514.0
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Wassel, Edward Richard , Watkins, Gerald Joseph
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F15/8084
摘要： A computer system is disclosed wherein an instruction is executed, the results of the execution of the instruction are stored, and, simultaneously with the execution of the instruction, information is generated and stored which is related to the results of the execution of the instruction. The results of the execution of the instruction may comprise a binary number. The information which is generated, simultaneously with the execution of the instruction, includes, inter-alia, a count of the number of binary "1" bits and binary "0" bits which constitute the binary number, and a set of addresses representing the address locations of each bit of the binary number which constitutes the stored results of the execution of the instruction. The set of addresses include a first set of addresses representing address locations for all the binary "1" bits and a second set of addresses representing address locations for all the binary "0" bits of the binary number. The first set of addresses are stored in a first portion of a memory, the second set of addresses being stored in a second portion of the memory. As a result, the information is immediately available upon completion of the execution of the instruction.
摘要翻译：公开了一种计算机系统，其中执行指令，存储指令的执行结果，并且与执行指令同时生成并存储与指令的执行结果有关的信息。执行指令的结果可以包括二进制数。与指令的执行同时产生的信息尤其包括构成二进制数的二进制“1”比特和二进制“0”比特数的计数，以及一组代表构成执行指令的存储结果的二进制数的每个位的地址位置。地址集合包括表示所有二进制“1”位的地址位置的第一组地址，以及表示二进制数的所有二进制“0”位的地址位置的第二组地址。第一组地址存储在存储器的第一部分中，第二组地址存储在存储器的第二部分中。因此，完成执行指令后，信息将立即可用。

2. 发明授权

EP0126247B1 Computer system 失效
标题翻译：电脑系统
公开(公告)号：EP0126247B1
公开(公告)日：1991-02-27
申请号：EP84103514.0
申请日：1984-03-30
申请人： International Business Machines Corporation
发明人： Wassel, Edward Richard , Watkins, Gerald Joseph
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F15/8084

3. 发明公开

EP0195245A2 A high performance parallel vector processor having a modified vector register/element processor configuration 失效
标题翻译：高性能并行矢量处理器具有修饰的注册/元件处理器配置。
公开(公告)号：EP0195245A2
公开(公告)日：1986-09-24
申请号：EP86101870.3
申请日：1986-02-14
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： G06F15/347 , G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007
摘要： A parallel vector processor is disclosed. The vector processor comprises a plurality of vector registers, each vector register being subdivided in a plurality of smaller registers. A vector is stored in each vector register, the vector comprising a plurality of elements. The elements of the vectors are assigned for storage in the smaller registers of the vector register. In the parallel vector processor of the present invention, assume that each vector register is sub- divided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not await the completion of the processing of a first element stored in the same vector register.

4. 发明公开

EP0195245A3 A high performance parallel vector processor having a modified vector register/element processor configuration 失效
标题翻译：具有修改的矢量寄存器/元件处理器配置的高性能并行矢量处理器
公开(公告)号：EP0195245A3
公开(公告)日：1989-05-03
申请号：EP86101870.3
申请日：1986-02-14
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： G06F15/347 , G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007
摘要： A parallel vector processor is disclosed. The vector processor comprises a plurality of vector registers, each vector register being subdivided in a plurality of smaller registers. A vector is stored in each vector register, the vector comprising a plurality of elements. The elements of the vectors are assigned for storage in the smaller registers of the vector register. In the parallel vector processor of the present invention, assume that each vector register is sub- divided into M smaller registers. The first successive M elements of an N element vector are assigned for storage in the M smaller registers of the vector register. An element processor is connected to each smaller register. Therefore, the first successive M elements of the N element vector are processed by the element processors 1 through M. The second successive M elements of the N element vector are assigned for storage in the same M smaller registers. The third successive M elements of the N element vector are assigned for storage in the M smaller registers. The second and third successive M elements of the N element vector are each processed by the element processors 1 through M. As a result, if the elements of a vector must be processed sequentially, when a second element, stored in a smaller register, is ready for processing by an element processor, the processing of the second element need not await the completion of the processing of a first element stored in the same vector register.

5. 发明公开

EP0167047A2 Latch circuit 失效
标题翻译： Verriegelungsschaltung。
公开(公告)号：EP0167047A2
公开(公告)日：1986-01-08
申请号：EP85107438.5
申请日：1985-06-19
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： H03K3/037
CPC分类号： H03K3/037 , G01R31/31725 , G01R31/318572 , G01R31/318594
摘要： The latch circuit comprises output latch circuit means (30) and input data steering and locking means (10) responsive to a clock pulse train transmitted via a clock pulse train transmitting means, responsive to a pulse transmitted via a system gate, and responsive to input data transmitted via an input data line for steering input data from the input data line to an input of said output latch circuit means (30) and for locking the binary state of said input data appearing at said input of said output latch at a value which it possessed when a clock pulse of said clock pulse train becomes active.
A transfer gate means (20) is interconnecting said input data steering and locking means (10) to said output latch circuit means (30) for transferring said input data from the input of said output latch to an output of said output latch in response to a pulse transmitted via the system gate during the active transmission of said clock pulse thereby changing the output binary value of said output latch circuit means (30).
This latch circuit functions as a level sensitive scan design (LSSD) latch, that is, the latch circuit possesses a scan capability; however, the scan capability of the latch circuit is implemented in association with a single clock line. This latch circuit also functions as a D-type latch, that is, the output of the latch circuit changes state when a clock pulse from the clock line is received.
摘要翻译：锁存电路包括输出锁存电路装置（30）和响应于经由时钟脉冲串发送装置发送的时钟脉冲串的输入数据转向和锁定装置（10），响应于经由系统门传输的脉冲，并响应于输入经由用于将输入数据从输入数据线转向输入锁存电路装置（30）的输入的输入数据线传送的数据，并且用于将出现在所述输出锁存器的所述输入处的所述输入数据的二进制状态锁定在当所述时钟脉冲串的时钟脉冲变为有效时。传输门装置（20）将所述输入数据转向和锁定装置（10）互连到所述输出锁存电路装置（30），用于将所述输入数据从所述输出锁存器的输入传送到所述输出锁存装置响应于在所述时钟脉冲的有效传输期间经由系统门传输的脉冲的输出锁存器，从而改变所述输出锁存电路装置（30）的输出二进制值。该锁存电路用作电平敏感扫描设计（LSSD）锁存器，即锁存电路具有扫描能力; 然而，锁存电路的扫描能力与单个时钟线相关联地被实现。该锁存电路也用作D型锁存器，即当接收到来自时钟线的时钟脉冲时，锁存电路的输出改变状态。

6. 发明授权

EP0244676B1 Method for improving system operation by programming micro word cycle length 失效
标题翻译：一种用于通过微字的周期持续时间的编程操作系统改进方法。
公开(公告)号：EP0244676B1
公开(公告)日：1994-09-14
申请号：EP87105554.7
申请日：1987-04-14
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： G06F9/22
CPC分类号： G06F9/223

7. 发明授权

EP0167047B1 Latch circuit 失效
标题翻译：锁定电路
公开(公告)号：EP0167047B1
公开(公告)日：1991-10-16
申请号：EP85107438.5
申请日：1985-06-19
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： H03K3/037
CPC分类号： H03K3/037 , G01R31/31725 , G01R31/318572 , G01R31/318594

8. 发明授权

EP0195245B1 A high performance parallel vector processor having a modified vector register/element processor configuration 失效
标题翻译：具有修改的矢量寄存器/元件处理器配置的高性能并行矢量处理器
公开(公告)号：EP0195245B1
公开(公告)日：1992-09-30
申请号：EP86101870.3
申请日：1986-02-14
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： G06F15/347 , G06F15/76
CPC分类号： G06F15/8092 , G06F15/8007

9. 发明公开

EP0244676A3 Method for improving system operation by programming micro word cycle length 失效
标题翻译：通过编程微信周期长度改进系统运行的方法
公开(公告)号：EP0244676A3
公开(公告)日：1991-12-04
申请号：EP87105554.7
申请日：1987-04-14
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： G06F9/22
CPC分类号： G06F9/223
摘要： A method for optimizing performance in a fixed clock rate computer system. A control word is provided having a control portion for operational instructions and a programmable timing portion. The programmable timing portion includes a value representative of the sum of execution time and inter-execution delay time. A counter (22i) is provided for receiving the value representative of the execution and inter-execution times. The counter is capable of generating a signal (EOS) to indicate an end of decrementing operation. The operational instructions are executed simultaneously with the processing of the time value in the counter so that a subsequent instruction is executed only when an end of operation signal is received from the counter.

10. 发明公开

EP0167047A3 Latch circuit 失效
标题翻译：锁定电路
公开(公告)号：EP0167047A3
公开(公告)日：1988-04-20
申请号：EP85107438
申请日：1985-06-19
申请人： International Business Machines Corporation
发明人： Ngai, Chuck Hong , Watkins, Gerald Joseph
IPC分类号： H03K03/037
CPC分类号： H03K3/037 , G01R31/31725 , G01R31/318572 , G01R31/318594
摘要： The latch circuit comprises output latch circuit means (30) and input data steering and locking means (10) responsive to a clock pulse train transmitted via a clock pulse train transmitting means, responsive to a pulse transmitted via a system gate, and responsive to input data transmitted via an input data line for steering input data from the input data line to an input of said output latch circuit means (30) and for locking the binary state of said input data appearing at said input of said output latch at a value which it possessed when a clock pulse of said clock pulse train becomes active. A transfer gate means (20) is interconnecting said input data steering and locking means (10) to said output latch circuit means (30) for transferring said input data from the input of said output latch to an output of said output latch in response to a pulse transmitted via the system gate during the active transmission of said clock pulse thereby changing the output binary value of said output latch circuit means (30). This latch circuit functions as a level sensitive scan design (LSSD) latch, that is, the latch circuit possesses a scan capability; however, the scan capability of the latch circuit is implemented in association with a single clock line. This latch circuit also functions as a D-type latch, that is, the output of the latch circuit changes state when a clock pulse from the clock line is received.

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