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1. 发明授权

EP0095598B1 Multiprocessor with independent direct cache-to-cache data transfers 失效
标题翻译：具有独立直接高速缓存数据传输的多处理器
公开(公告)号：EP0095598B1
公开(公告)日：1989-09-06
申请号：EP83104482.1
申请日：1983-05-06
申请人： International Business Machines Corporation
发明人： Krygowski, Matthew Anthony , Messina, Benedicto Umberto , Silkman, William Dean
IPC分类号： G06F12/08
CPC分类号： G06F12/0822

2. 发明公开

EP0495167A3 Multiple asynchronous request handling 失效
标题翻译：多个异步请求处理
公开(公告)号：EP0495167A3
公开(公告)日：1996-03-06
申请号：EP91119001.5
申请日：1991-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bean, Bradford Mason , Bierce, Anne Elizabeth , Cristensen, Neal Taylor , Clark, Leo James , Jones, Christine Comins , Krygowski, Matthew Anthony , Reick, Kevin Franklin
IPC分类号： G06F9/38 , G06F13/16
CPC分类号： G06F9/3824
摘要： Plural requests for storage accessing are processed in plural stages of a storage-request pipeline. Pipeline processing is not interrupted when one or more requests must wait for a resource to start its processing, or when a pipeline stage must process for a long period in relation to the time allocated for a processing operation in the pipeline. Waiting is done in a wait path connected to a particular processing stage in the pipeline. A request is shunted from the pipeline into a wait path when processing the request in the pipeline would delay pipeline processing. When the wait has ended, a request re-enters the pipeline from its wait path. The pipeline is provided in a multiprocessor (MP) in which storage requests are provided asynchronously to a tightly coupled system storage and usually may be handled and processed asynchronously by the pipeline. The pipeline output may direct the processed requests to a shared intermediate cache or to the system main storage.

3. 发明公开

EP0507063A1 Cross-invalidate directory method and means 失效
标题翻译： Verfahren und Vorrichtungfürein Verzeichnis zum kreuzweisenUngültigerklären。
公开(公告)号：EP0507063A1
公开(公告)日：1992-10-07
申请号：EP92102390.9
申请日：1992-02-13
申请人： International Business Machines Corporation
发明人： Gannon, Patrick Melvin , Ignatowski, Michael , Krygowski, Matthew Anthony , Liu, Lishing , Price, Donald Walter , Rodiger, William King , Salyer, Gregory , Ting, Yee-Ming , Witt, Michael Paul
IPC分类号： G06F12/08
CPC分类号： G06F12/082 , G06F12/0811
摘要： A coherence directory and its methods of operation are disclosed for private processor caches in a multiple processor system to control data coherence in the system. It provides cross-invalidate (XI) controls for the assignment of exclusive and public ownership to data units in the processor caches, including required cross-invalidation of data units among the processor caches to obtain data coherence in the system in an efficient manner. The coherence directory can be used in a multiple processor system with or without any shared second level (L2) cache, shared or private. When a shared L2 cache is used to improve system access time, the coherence directory can also be used as the second level directory for the shared L2 cache and eliminate the need for any additional L2 directory(s).
摘要翻译：公开了一种在多处理器系统中的专用处理器高速缓存的相干目录及其操作方法，以控制系统中的数据一致性。它提供了交叉无效（XI）控制，用于将处理器高速缓存中的数据单元分配给专用和公共所有权，包括处理器高速缓存中数据单元的所需交叉无效，以便以有效的方式获得系统中的数据一致性。可以在具有或不具有任何共享的第二级（L2）缓存，共享或私有的多处理器系统中使用相干目录。当使用共享的L2缓存来提高系统访问时间时，相干目录也可以用作共享L2缓存的第二级目录，并且不需要任何额外的L2目录。

4. 发明授权

EP0166341B1 Multiprocessor system with fast path means for storage accesses 失效
标题翻译：具有存储访问快速路径的多处理器系统
公开(公告)号：EP0166341B1
公开(公告)日：1992-05-06
申请号：EP85107439.3
申请日：1985-06-19
申请人： International Business Machines Corporation
发明人： Chiesa, George Louis , Krygowski, Matthew Anthony , Messina, Benedicto Umberto , Papanastasiou, Theodore Athanasios
IPC分类号： G06F12/08
CPC分类号： G06F12/0817

5. 发明公开

EP0095598A3 Multiprocessor with independent direct cache-to-cache data transfers 失效
标题翻译：具有独立直接高速缓存数据传输的多处理器
公开(公告)号：EP0095598A3
公开(公告)日：1986-07-16
申请号：EP83104482
申请日：1983-05-06
申请人： International Business Machines Corporation
发明人： Krygowski, Matthew Anthony , Messina, Benedicto Umberto , Silkman, William Dean
IPC分类号： G11C09/06
CPC分类号： G06F12/0822
摘要： In a data processing system having multiple processors with individual cache stores, a cross-interrogation is made in other caches if requested data is not found in the local associated cache. Data paths (67, 74, 83, 86, 201, 202, 203, 207, 208) and communication controls (20, 21, 22, 23, 50, 76, 77) are provided to enable direct cache-to-cache and cache-to-channel data transfers thus saving main storage accesses and the necessity to wait for main storage availability.

6. 发明公开

EP0495167A2 Multiple asynchronous request handling 失效
标题翻译： Behandlung von mehrfach asynchronen Anforderungen。
公开(公告)号：EP0495167A2
公开(公告)日：1992-07-22
申请号：EP91119001.5
申请日：1991-11-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bean, Bradford Mason , Bierce, Anne Elizabeth , Cristensen, Neal Taylor , Clark, Leo James , Jones, Christine Comins , Krygowski, Matthew Anthony , Reick, Kevin Franklin
IPC分类号： G06F9/38 , G06F13/16
CPC分类号： G06F9/3824
摘要： Plural requests for storage accessing are processed in plural stages of a storage-request pipeline. Pipeline processing is not interrupted when one or more requests must wait for a resource to start its processing, or when a pipeline stage must process for a long period in relation to the time allocated for a processing operation in the pipeline. Waiting is done in a wait path connected to a particular processing stage in the pipeline. A request is shunted from the pipeline into a wait path when processing the request in the pipeline would delay pipeline processing. When the wait has ended, a request re-enters the pipeline from its wait path. The pipeline is provided in a multiprocessor (MP) in which storage requests are provided asynchronously to a tightly coupled system storage and usually may be handled and processed asynchronously by the pipeline. The pipeline output may direct the processed requests to a shared intermediate cache or to the system main storage.
摘要翻译：存储访问的多个请求在存储请求流水线的多个阶段中被处理。当一个或多个请求必须等待资源开始处理时，或当流水线阶段必须相对于分配给流水线中的处理操作的时间长时间处理时，流水线处理不会中断。等待在连接到流水线中的特定处理阶段的等待路径中完成。当处理流水线中的请求将延迟流水线处理时，请求从流水线分流到等待路径。当等待结束时，请求从其等待路径重新输入流水线。流水线设置在多处理器（MP）中，其中存储请求被异步地提供给紧耦合的系统存储器，并且通常可以由流水线异步处理和处理。流水线输出可以将处理的请求定向到共享中间缓存或系统主存储。

7. 发明公开

EP0166341A3 Multiprocessor system with fast path means for storage accesses 失效
标题翻译：用于存储访问的快速路径的多处理器系统
公开(公告)号：EP0166341A3
公开(公告)日：1988-08-24
申请号：EP85107439
申请日：1985-06-19
申请人： International Business Machines Corporation
发明人： Chiesa, George Louis , Krygowski, Matthew Anthony , Messina, Benedicto Umberto , Papanastasiou, Theodore Athanasios
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A fast path (comprising control and data busses) directly connects between a storage controller (18) in a main storage (21) and a requestor (CPU). The fast path (12) is in parallel with the bus path (11, 16, 14) normally provided through the storage hierarchy between the requestor (CPU) and the storage controller (18). The fast path (12) may bypass intermediate levels in the storage hierarchy. The fast path (12) is used at least for fetch requests from the requestor (CPU), since fetch request have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path (12) in a system to decrease the peak loads on the normal path (11, 16, 14). A requestor (CPU) using the fast path (12) and to the normal path (11, 16, 14) in a system controller element (16). The request through the fast path (12) gets to the main storage (21) before the same request gets through the system controller element, but may be ignored by the storage (21) if the latter is busy. If accepted, the storage (21) can start its accessing controls sooner for a fast path request than if the request is received from the normal path. Every request must use controlled cross-interrogate (17) and storage protect (19) resources. Fast path request SP controls, the SCE priority controls, and by the storage element priority controls. When the accessed data is ready to be sent by the main storage (21), it can be sent to the requestor (CPU) faster on the fast path data bus (12) than on the SCE data bus (11,16,14). The fast path data bus (12) may be used to transfer data for requests ignored from the fast path.

8. 发明公开

EP0166341A2 Multiprocessor system with fast path means for storage accesses 失效
标题翻译：与Schnellwegmitteln多处理器布置用于存储器存取。
公开(公告)号：EP0166341A2
公开(公告)日：1986-01-02
申请号：EP85107439.3
申请日：1985-06-19
申请人： International Business Machines Corporation
发明人： Chiesa, George Louis , Krygowski, Matthew Anthony , Messina, Benedicto Umberto , Papanastasiou, Theodore Athanasios
IPC分类号： G06F12/08
CPC分类号： G06F12/0817
摘要： A fast path (comprising control and data busses) directly connects between a storage controller (18) in a main storage (21) and a requestor (CPU). The fast path (12) is in parallel with the bus path (11, 16, 14) normally provided through the storage hierarchy between the requestor (CPU) and the storage controller (18). The fast path (12) may bypass intermediate levels in the storage hierarchy. The fast path (12) is used at least for fetch requests from the requestor (CPU), since fetch request have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path (12) in a system to decrease the peak loads on the normal path (11, 16, 14). A requestor (CPU) using the fast path (12) and to the normal path (11, 16, 14) in a system controller element (16). The request through the fast path (12) gets to the main storage (21) before the same request gets through the system controller element, but may be ignored by the storage (21) if the latter is busy. If accepted, the storage (21) can start its accessing controls sooner for a fast path request than if the request is received from the normal path. Every request must use controlled cross-interrogate (17) and storage protect (19) resources. Fast path request SP controls, the SCE priority controls, and by the storage element priority controls. When the accessed data is ready to be sent by the main storage (21), it can be sent to the requestor (CPU) faster on the fast path data bus (12) than on the SCE data bus (11,16,14). The fast path data bus (12) may be used to transfer data for requests ignored from the fast path.

9. 发明公开

EP0095598A2 Multiprocessor with independent direct cache-to-cache data transfers 失效
标题翻译： Mehrfachprozessor mitunabhängigerdirekter“Cache”zu“Cache”-Datenübertragung。
公开(公告)号：EP0095598A2
公开(公告)日：1983-12-07
申请号：EP83104482.1
申请日：1983-05-06
申请人： International Business Machines Corporation
发明人： Krygowski, Matthew Anthony , Messina, Benedicto Umberto , Silkman, William Dean
IPC分类号： G06F12/08
CPC分类号： G06F12/0822
摘要： In a data processing system having multiple processors with individual cache stores, a cross-interrogation is made in other caches if requested data is not found in the local associated cache. Data paths (67, 74, 83, 86, 201, 202, 203, 207, 208) and communication controls (20, 21, 22, 23, 50, 76, 77) are provided to enable direct cache-to-cache and cache-to-channel data transfers thus saving main storage accesses and the necessity to wait for main storage availability.
摘要翻译：在具有具有各个高速缓存存储器的多个处理器的数据处理系统中，如果在本地关联高速缓存中没有找到请求的数据，则在其他高速缓存中进行交叉询问。提供数据路径（67,74,83,86,201,202,203,207,208）和通信控制（20,21,22,23,50,76,77）以实现直接缓存到缓存和高速缓存 - 频道数据传输，从而节省主存储访问以及等待主存储可用性的必要性。

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