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1. 发明授权

EP0089504B1 Method for making an integrated circuit with multiple base width transistor structures 失效
标题翻译：用多个基极宽度晶体管结构制作集成电路的方法
公开(公告)号：EP0089504B1
公开(公告)日：1989-08-16
申请号：EP83101756.1
申请日：1983-02-23
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Dorler, Jack Arthur , Gaur, Santosh Prasad , Lechaton, John S. , Mosley, Joseph Michael , Srinivasan, Gurumakonda R.
IPC分类号： H01L21/82 , H01L27/06
CPC分类号： H01L27/0825 , H01L21/3065 , H01L21/8222 , H01L29/1004

2. 发明公开

EP0089504A3 Method for making an integrated circuit with multiple base width transistor structures 失效
标题翻译：用多个基极宽度晶体管结构制造集成电路的方法
公开(公告)号：EP0089504A3
公开(公告)日：1986-09-10
申请号：EP83101756
申请日：1983-02-23
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Dorler, Jack Arthur , Gaur, Santosh Prasad , Lechaton, John S. , Mosley, Joseph Michael , Srinivasan, Gurumakonda R.
IPC分类号： H01L21/82 , H01L27/06
CPC分类号： H01L27/0825 , H01L21/3065 , H01L21/8222 , H01L29/1004
摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a valuable degree of freedom for design of integrated circuits. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter (34, 35) formation, the base area (22) which is to be the emitter (34) of the selected region havingthe very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitters (34, 35) and rest of the metallization.

3. 发明授权

EP0005728B1 Verfahren zum Herstellen eines lateralen PNP- oder NPN-Transistors mit hoher Verstärkung und dadurch hergestellter Transistor 失效
标题翻译：制造具有高增益和晶体管的横向PNP或NPN晶体管的方法
公开(公告)号：EP0005728B1
公开(公告)日：1982-02-03
申请号：EP79101267.7
申请日：1979-04-26
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad , Pogge, Hans Bernhard
IPC分类号： H01L27/08 , H01L29/72 , H01L21/76
CPC分类号： H01L27/0821 , H01L21/76232 , H01L29/735 , Y10S148/031 , Y10S148/051 , Y10S148/085

4. 发明公开

EP0072412A3 Dynamic semiconductor memory cell 失效
标题翻译：动态半导体存储单元
公开(公告)号：EP0072412A3
公开(公告)日：1984-04-25
申请号：EP82105757
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad
IPC分类号： H01L27/10 , G11C11/24
CPC分类号： H01L27/1023 , G11C11/34 , H01L27/1028 , H01L27/115
摘要： A dynamic memory cell has a P+ injector region (48) surrounded by an N+ region (44) in an N- layer (30) on an N+ layer (20). The injector region (48) is placed between N+ source and drain regions (38, 40). Holes injected into the N-layer (30) are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

5. 发明公开

EP0072412A2 Dynamic semiconductor memory cell 失效
标题翻译：动态半导体存储器单元。
公开(公告)号：EP0072412A2
公开(公告)日：1983-02-23
申请号：EP82105757.7
申请日：1982-06-29
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad
IPC分类号： H01L27/10 , G11C11/24
CPC分类号： H01L27/1023 , G11C11/34 , H01L27/1028 , H01L27/115
摘要： A dynamic memory cell has a P+ injector region (48) surrounded by an N+ region (44) in an N- layer (30) on an N+ layer (20). The injector region (48) is placed between N+ source and drain regions (38, 40). Holes injected into the N-layer (30) are trapped by the high-low junctions at the N+, N- interfaces and are detected by sensing the source-drain current. Current levels are used to establish binary one and zero levels in the cell. Four masks in an aligned procedure simplify fabrication.

6. 发明公开

EP0065133A2 Schottky barrier diode with a guard ring and method of making same 失效
标题翻译： Schottky-Sperrschichtdiode mit Schutzring und Verfahren zu ihrer Herstellung。
公开(公告)号：EP0065133A2
公开(公告)日：1982-11-24
申请号：EP82103562.3
申请日：1982-04-27
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad , Mauer IV, John Lester
IPC分类号： H01L29/91
CPC分类号： H01L29/872
摘要： The Schottky barrier diode having a self-aligned guard ring comprises a dielectric layer (3) on a silicon substrate said layer (3) having a substantially vertically walled hole therein, a doped silicon lining (5) being of uniform width covering the silicon along the walls of said hole and contact metal (7) on said substrate exposed within the inner perimeter of that lining (5).
To produce such a diode a hole ist etched anisotropically into a dielectric layer (3) on a silicon substrate. Then a doped silicon layer (4) is deposited which is reactively ion etched, to expose said substrate through said hole. By heating the dopant in the remainder of said silicon layer (4) is diffused into the substrate. Onto the exposes substrate metal (7) is applied.
摘要翻译：具有自对准保护环的肖特基势垒二极管包括在硅衬底上的介电层（3），所述层（3）上具有基本上垂直的壁孔，掺杂硅衬层（5）具有均匀的宽度，覆盖硅所述孔的壁和所述基底上的接触金属（7）暴露在该衬里（5）的内周边内。为了制造这样的二极管，将各向异性地蚀刻到硅衬底上的电介质层（3）中的孔。然后沉积掺杂的硅层（4），其被反应离子蚀刻，以通过所述孔暴露所述衬底。通过加热所述硅层（4）的其余部分中的掺杂剂扩散到衬底中。在曝光的基底金属（7）上施加。

7. 发明授权

EP0089503B1 Method for making a high performance bipolar transistor in an integrated circuit 失效
标题翻译：在集成电路中制造高性能双极晶体管的方法
公开(公告)号：EP0089503B1
公开(公告)日：1989-09-13
申请号：EP83101755.3
申请日：1983-02-23
申请人： International Business Machines Corporation
发明人： Gaur, Santosh Prasad , Lechaton, John S. , Srinivasan, Gurumakonda R.
IPC分类号： H01L29/10 , H01L29/72
CPC分类号： H01L29/1004 , H01L21/3065 , H01L29/7325

8. 发明公开

EP0089503A3 Method for making a high performance bipolar transistor in an integrated circuit 失效
标题翻译：在集成电路中制造高性能双极晶体管的方法
公开(公告)号：EP0089503A3
公开(公告)日：1986-09-17
申请号：EP83101755
申请日：1983-02-23
申请人： International Business Machines Corporation
发明人： Gaur, Santosh Prasad , Lechaton, John S. , Srinivasan, Gurumakonda R.
IPC分类号： H01L29/10 , H01L29/72
CPC分类号： H01L29/1004 , H01L21/3065 , H01L29/7325
摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The biplar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, a portion of the base area (22) wherein the emitter region (34) is planned to be formed is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers (24, 26) with the emitter opening (30) therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter (34) is etched, and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.

9. 发明公开

EP0089504A2 Method for making an integrated circuit with multiple base width transistor structures 失效
标题翻译：一种用于制备包括具有不同宽度的碱晶体管结构的集成电路的过程。
公开(公告)号：EP0089504A2
公开(公告)日：1983-09-28
申请号：EP83101756.1
申请日：1983-02-23
申请人： International Business Machines Corporation
发明人： Bhatia, Harsaran Singh , Dorler, Jack Arthur , Gaur, Santosh Prasad , Lechaton, John S. , Mosley, Joseph Michael , Srinivasan, Gurumakonda R.
IPC分类号： H01L21/82 , H01L27/06
CPC分类号： H01L27/0825 , H01L21/3065 , H01L21/8222 , H01L29/1004
摘要： A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a valuable degree of freedom for design of integrated circuits. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter (34, 35) formation, the base area (22) which is to be the emitter (34) of the selected region havingthe very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitters (34, 35) and rest of the metallization.

10. 发明公开

EP0005728A1 Verfahren zum Herstellen eines lateralen PNP- oder NPN-Transistors mit hoher Verstärkung und dadurch hergestellter Transistor 失效
标题翻译：制造具有高增益和由此产生晶体管横向PNP或NPN晶体管的方法。
公开(公告)号：EP0005728A1
公开(公告)日：1979-12-12
申请号：EP79101267.7
申请日：1979-04-26
申请人： International Business Machines Corporation
发明人： Anantha, Narasipur Gundappa , Bhatia, Harsaran Singh , Gaur, Santosh Prasad , Pogge, Hans Bernhard
IPC分类号： H01L27/08 , H01L29/72 , H01L21/76
CPC分类号： H01L27/0821 , H01L21/76232 , H01L29/735 , Y10S148/031 , Y10S148/051 , Y10S148/085
摘要： Verfahren zum Herstellen lateraler PNP- oder NPN-Transistoren in isolierten, monokristallinen Siliciumbereichen, die durch Siliciumdioxid-Isolationszonen isoliert sind, wobei die PNP- oder NPN-Transistoren innerhalb der isolierten monokristallinen Zone teilweise unterhalb der Oberfläche des Halbleiters gebildet werden. Die P-Emitter oder N-Emitterdiffusion wird über dem Abschnitt der Siliciumdioxid-Schicht durchgeführt, die sich teilweise in die isolierte monokristalline Zone hinein erstreckt. Durch diesen Aufbau wird die vertikale Strominjektion herabgesetzt, so daß man eine relativ hohe (Beta) Verstärkung selbst bei kleinen Basis-Emitter-Spannungen erhält. Der durch dieses Verfahren erzeugte laterale PNP- oder NPN-Transistor liegt in einer isolierten monokristallinen Siliciumzone, wobei die Siliciumdioxid-Isolation die Zone umgibt und teilweise unterhalb der Oberfläche in die isolierte monokristalline Siliciumzone hineinreicht. Die P-Emitter- oder N-Emitter-Diffusion liegt über dem Abschnitt der Siliciumdioxid-Schicht, der sich teilweise in die monokristalline isolierte Zone hineinerstreckt.
摘要翻译：在所述分离的单晶硅区域，其通过二氧化硅隔离区绝缘，其中所述PNP或NPN晶体管被分离的单晶区部分内的半导体的表面下方形成的制造横向PNP或NPN晶体管的方法。 P型发射极和N型发射极扩散在二氧化硅层，其在所述分离的单晶区内部部分延伸的部分执行。通过这种结构中，垂直电流注入被减少，使得相对高的（测试版）接收甚至具有小基极 - 发射极电压增益。由该方法生产的横向PNP或NPN晶体管处于绝缘单晶硅区，所述周围区域并且部分地二氧化硅绝缘表面的下方在所述分离的单晶硅区延伸。在p-发射极或N极 - 发射极扩散超过二氧化硅层，其部分地延伸到所述单晶分离区域的该部分。

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