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1. 发明公开

EP3879410A1 TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON SET OF INTERCONNECT CONNECTORS 审中-公开
公开(公告)号：EP3879410A1
公开(公告)日：2021-09-15
申请号：EP21168844.5
申请日：2017-06-14
申请人： INTEL Corporation
发明人： WAGH, Mahesh , MYERS, Mark S. , VAN DOREN, Stephen R. , ZIAKAS, Dimitrios , COURY, Bassam
IPC分类号： G06F13/38
摘要： The present disclosure provides an apparatus comprising a plurality of processing cores integrated onto multiple integrated circuit dies in a package, the plurality of processing cores to execute instructions and process data, memory logic to couple to a memory device, a coherent interconnect fabric to connect the plurality of processing cores and the memory logic and a physical, PHY, layer interface. The physical, PHY, layer interface comprising a plurality of connectors coupled to a plurality of data lanes, the plurality of connectors including a first subset of the connectors to communicate in accordance with a first interconnect protocol, a second subset of the connectors to communicate in accordance with a second interconnect protocol, and a third subset of the connectors to communicate in accordance with a third interconnect protocol. The apparatus comprising a first logical sub-block to encode data in accordance with the first interconnect protocol, a second logical sub-block to encode data in accordance with the second interconnect protocol and a third logical sub-block to encode data in accordance with the third interconnect protocol and a multiplexer. The multiplexer is to connect the first subset of connectors to the first logical sub-block, to connect the second subset of the connectors to the second logical sub-block, and to connect the third subset of the connectors to the third logical sub-block. The apparatus comprising a first transaction layer to communicate data between the coherent interconnect fabric and the first logical sub-block in accordance with the first interconnect protocol; a second transaction layer to communicate data between the coherent interconnect fabric and the second logical sub-block in accordance with the second interconnect protocol; and a third transaction layer to communicate data between the coherent interconnect fabric and the third logical sub-block in accordance with the third interconnect protocol.

2. 发明公开

EP3506087A1 SPATIAL AND TEMPORAL MERGING OF REMOTE ATOMIC OPERATIONS 有权
公开(公告)号：EP3506087A1
公开(公告)日：2019-07-03
申请号：EP18209326.0
申请日：2018-11-29
申请人： INTEL Corporation
发明人： HUGHES, Christopher J. , NUZMAN, Joseph , SVENNEBRING, Jonas , JAYASIMHA, Doddaballapur N. , SURY, Samantika S. , KOUFATY, David A. , MCDONNELL, Niall D. , LIU, Yen-Cheng , VAN DOREN, Stephen R. , ROBINSON, Stephen J.
IPC分类号： G06F9/30 , G06F12/08
摘要： Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

3. 发明公开

EP3488352A1 TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON SET OF INTERCONNECT CONNECTORS 审中-公开
公开(公告)号：EP3488352A1
公开(公告)日：2019-05-29
申请号：EP17831476.1
申请日：2017-06-14
申请人： INTEL Corporation
发明人： WAGH, Mahesh , MYERS, Mark S. , VAN DOREN, Stephen R. , ZIAKAS, Dimitrios , COURY, Bassam
IPC分类号： G06F13/42

4. 发明公开

EP4089531A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 审中-实审
公开(公告)号：EP4089531A1
公开(公告)日：2022-11-16
申请号：EP22180798.5
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/38 , G06F12/08
摘要： The present disclosure provides an apparatus comprising an accelerator; a local memory comprising a plurality of stacked dynamic random access memory, DRAM, dies; a silicon bridge to couple the accelerator to the plurality of stacked DRAM dies, wherein connections between the accelerator and the plurality of stacked DRAM dies run through the silicon bridge. The accelerator comprising a plurality of processing elements to perform processing tasks allocated by an external processor; a cache coherent interface to couple the accelerator to the external processor, the cache coherent interface to ensure that data stored in the local memory and/or an accelerator cache is coherent with data stored in a system memory and caches of the external processor; and logic to map a virtual memory space to heterogeneous forms of physical system memory including the local memory and the system memory, the accelerator and the external processor to both use the virtual memory space to access corresponding portions of the local memory and the system memory.

5. 发明公开

EP4120070A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 有权
公开(公告)号：EP4120070A1
公开(公告)日：2023-01-18
申请号：EP22193012.6
申请日：2016-12-31
申请人： INTEL Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/30
摘要： The present disclosure provides a method and an apparatus comprising a decoder to decode an enqueue command instruction, execution circuitry, where execution of the enqueue command instruction causes the execution circuitry to: generate a work descriptor based, at least in part, on data from a source operand of the enqueue command instruction, the work descriptor comprising a plurality of fields including an operation field to specify one or more operations to be performed, a flag to indicate whether the work descriptor can be processed in parallel with one or more other work descriptors, and an address field associated with the one or more operations and to store the work descriptor to a work queue.

6. 发明公开

EP3812900A1 SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING 有权
公开(公告)号：EP3812900A1
公开(公告)日：2021-04-28
申请号：EP20207505.7
申请日：2016-12-31
申请人： Intel Corporation
发明人： SANKARAN, Rajesh M. , NEIGER, Gilbert , RANGANATHAN, Narayan , VAN DOREN, Stephen R. , NUZMAN, Joseph , MCDONNELL, Niall D. , O'HANLON, Michael A. , MOSUR, Lokpraveen B. , DRYSDALE, Tracy Garrett , NURVITADHI, Eriko , MISHRA, Asit K. , VENKATESH, Ganesh , MARR, Deborah T. , CARTER, Nicholas P. , PEARCE, Jonathan D. , GROCHOWSKI, Edward T. , GRECO, Richard J. , VALENTINE, Robert , CORBAL, Jesus , FLETCHER, Thomas D. , BRADFORD, Dennis R. , MANLEY, Dwight P. , CHARNEY, Mark J. , COOK, Jeffrey J. , CAPRIOLI, Paul , YAMADA, Koichi , GLOSSOP, Kent D. , SHEFFIELD, David B.
IPC分类号： G06F9/48 , G06F9/38
摘要： The present disclosure provides apparatus comprising a silicon interposer, a communication fabric, an accelerator die comprising a plurality of computing elements to simultaneously perform operations on a plurality of matrix data elements. The apparatus comprising a plurality of dot-product engines, the plurality of dot-product engines to compute a plurality of dot products on the matrix data elements to generate a plurality of result matrix data elements, a buffer or cache to store a plurality of matrix data elements a memory controller coupled to the communication fabric and a stacked DRAM that stacks a plurality of DRAM dies vertically on the silicon interposer substrate coupled to the accelerator die.

8. 发明公开

EP3084608A1 SCALABLY MECHANISM TO IMPLEMENT AN INSTRUCTION THAT MONITORS FOR WRITES TO AN ADDRESS 有权
标题翻译：可伸缩的机制用于订购监控台操作来一个地址实现
公开(公告)号：EP3084608A1
公开(公告)日：2016-10-26
申请号：EP14849874.4
申请日：2014-10-03
申请人： Intel Corporation
发明人： LIU, Yen-Cheng , FAHIM, Bahaa , HALLNOR, Erik G. , CHAMBERLAIN, Jeffrey D. , VAN DOREN, Stephen R. , JUAN, Antonio
IPC分类号： G06F11/30 , G06F12/06
CPC分类号： G06F12/084 , G06F9/30087 , G06F9/3009 , G06F9/46 , G06F12/0811 , G06F12/0833 , G06F12/0846 , G06F2212/1016
摘要： A processor includes a cache-side address monitor unit corresponding to a first cache portion of a distributed cache that has a total number of cache-side address monitor storage locations less than a total number of logical processors of the processor. Each cache-side address monitor storage location is to store an address to be monitored. A core-side address monitor unit corresponds to a first core and has a same number of core-side address monitor storage locations as a number of logical processors of the first core. Each core-side address monitor storage location is to store an address, and a monitor state for a different corresponding logical processor of the first core. A cache-side address monitor storage overflow unit corresponds to the first cache portion, and is to enforce an address monitor storage overflow policy when no unused cache-side address monitor storage location is available to store an address to be monitored.

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